MSquare's IO Die product, ML100, contains UCIe, HBM (PHY and controller), NOC, RISC-V CPU, and HBM3 DRAM. Paired with a SoC that integrates UCIe, the ML100 facilitates the conversion between international standard UCIe and HBM3 protocols, jointly accomplishing read and write operations on HBM3 chips. The CPU features a 32-bit RISC-V core, with a clock speed of 800 MHz, includes 1MB of built-in SRAM, and configurable with interrupt register, clock reset register, interrupt exception status registers, as well as access to a global register space.

ML100 integrates an efficient Die-to-Die interconnect IP, adhering to the standard UCIe 1.1 protocol. It supports both standard and advanced packaging technologies, with data transfer rates up to 32 GT/s per lane, and can deliver up to 4 Tbps of bandwidth in multi-module configurations. The UCIe controller supports the standard AXI4.0 interface protocol, enabling ultra-low latency high-speed interconnect between two chips. The ML100 also integrates an HBM3 memory processing subsystem that supports the standard HBM3 JESD238 protocol, with support for a maximum transfer rate of 6400 Mbps, achieving a complete high-speed, high-bandwidth memory solution.