安富利的人说使用Vivado自己的仿真器进行仿真，可是对于新手来说，还是觉得用ModelSim仿真比较自由一点。在Vivado的工程设置里可以修改目标仿真器，我们可以选择使用ModelSim来仿真。
指定仿真工具可以直接在vivado里执行“Run Simulation”命令来启动ModelSim开始仿真
此时，会给出一个致命警告，因为xilinx库还没有提取。所以，根据前面图中提示，从vivado的tools菜单下选择编译库来提取Xilinx的ModelSim仿真库：
执行该命令弹出的界面如下图所示，如图所示，编译后的库存放在本工程之前设置的仿真路径下，为了一劳永逸，个人感觉应该可以和altera仿真库一般，在modelsim.ini文件里进行指定，这样以后每次启动ModelSim都会自动找到提取出来的Xilinx库。
这个库的提取时间还是比较长的，所以以后每次仿真都不能来这么一次，太耗时间了（大概30分钟，我想这才是人家不推荐使用ModelSim的原因吧）。库提取完成，再执行仿真（功能仿真），虽然没有错误，并也能看到波形，但是比较简单，应该是没有完备的测试激励：
仿真结果不对：
以上仿真是基于xapp1052参考设计，修改了vavido工程的仿真设置，选择了第三方仿真工具ModelSim，在“Run Simulation”里选择了功能仿真，这样在工程目录下自动生成了批处理文件以及脚本文件。仿真后的层次结构如下：
---------------------------------------------ModelSim警告信息------------------------------------------------- do {board_simulate.do} vsim -voptargs=""+acc"" -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.board xil_defaultlib.glbl # ** Warning: ../../../../pcie_7x_0_example.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v(1416): (vopt-2685) [TFMPC] - Too few port connections for 'pcie_top_i'. Expected 362, found 359. ** Warning: ../../../../pcie_7x_0_example.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v(1416): (vopt-2718) [TFMPC] - Missing connection for port 'pipe_rxstatus'. ** Warning: ../../../../pcie_7x_0_example.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v(1416): (vopt-2718) [TFMPC] - Missing connection for port 'pipe_rst_fsm'. ** Warning: ../../../../pcie_7x_0_example.srcs/sources_1/ip/pcie_7x_0/source/pcie_7x_0_core_top.v(1416): (vopt-2718) [TFMPC] - Missing connection for port 'sys_clk'. ** Note: (vopt-143) Recognized 1 FSM in module "BMD_128_RX_ENGINE(fast)". ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/simulation/dsport/pcie_2_1_rport_7x.v(1160): (vopt-2685) [TFMPC] - Too few port connections for 'pcie_top_i'. Expected 362, found 359. ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/simulation/dsport/pcie_2_1_rport_7x.v(1160): (vopt-2718) [TFMPC] - Missing connection for port 'pipe_rxstatus'. ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/simulation/dsport/pcie_2_1_rport_7x.v(1160): (vopt-2718) [TFMPC] - Missing connection for port 'pipe_rst_fsm'. ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/simulation/dsport/pcie_2_1_rport_7x.v(1160): (vopt-2718) [TFMPC] - Missing connection for port 'sys_clk'. ** Note: (vopt-143) Recognized 1 FSM in module "BMD_128_TX_ENGINE(fast)". ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/source/pcie_7x_0_gt_top_pipe_mode.v(264): (vopt-2685) [TFMPC] - Too few port connections for 'pipe_clock_i'. Expected 16, found 13. ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/source/pcie_7x_0_gt_top_pipe_mode.v(264): (vopt-2718) [TFMPC] - Missing connection for port 'CLK_OOBCLK'. ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/source/pcie_7x_0_gt_top_pipe_mode.v(264): (vopt-2718) [TFMPC] - Missing connection for port 'CLK_PCLK_SLAVE'. ** Warning: ../../../../pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/source/pcie_7x_0_gt_top_pipe_mode.v(264): (vopt-2718) [TFMPC] - Missing connection for port 'CLK_PCLK_SEL_SLAVE'. ** Note: (vopt-143) Recognized 1 FSM in module "PCIE_2_1(fast)".##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver.##### D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): in protected region. ** Warning: D:\Xilinx\Vivado\2018.3\data\secureip\pcie_2_1\pcie_2_1_002.vp(57): (vopt-2958) Implicit wire '' does not have any driver. # ** Warning: (vsim-3015) ../../../../pcie_7x_0_example.srcs/sources_1/imports/pcie_7x_0/bmd/pcie_app_7x_bmd.v(303): [PCDPC] - Port size (1) does not match connection size (32) for port 'trn_terrfwd'. The port definition is at: ../../../../pcie_7x_0_example.srcs/sources_1/imports/pcie_7x_0/bmd/axi_trn_top.v(117).
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