我们在用verilog或VHDL设计数字系统时，通常有行为描述和结构描述等多种表述方式，你写的verilog或VHDL源码都会被综合器软件转化为RTL级描述，而RTL级描述也是用verilog或VHDL语言来表述的，行为描述和结构描述,RTL级描述都是用verilog或VHDL语言来表述的，那么到底什么是硬件描述语言的RTL描述？或者它们有啥差别，还需要综合器费尽心思做这样的转换？
简单说，RTL描述就是用组合电路构成的数据通路+触发器的方式来等效描述你的原始设计，下图所示就是一个简单示意，触发器的输入只有数据通路的输出：
这种等效的描述转化，将复杂的数字系统逻辑结构归一化了，分为两类：组合电路构成的数据路径和触发器锁存，有点大家在数字电路课程里讲组合逻辑化简时，我们首先把逻辑表达式化为统一的最小项表达式，然后再在最小项表达式基础上做更多的其他工作，道理类似，一种统一的、一致性的、甚至可能是唯一的表述方式，更利于后续工作，这种RTL描述有很多好处：
“Many optimizations and analyses can be performed best at the RTL level. Examples include FSM detection and optimization, identification of memories or other larger building blocks and identification of shareable resources.”
“Note that RTL is the fifirst abstraction level in which the circuit is represented as a graph of circuit elements(registers and combinatorial cells) and signals. Such a graph, when encoded as list of cells and connections,is called a netlist.RTL synthesis is easy as each circuit node element in the netlist can simply be replaced with an equivalentgate-level circuit. However, usually the term RTL synthesis does not only refer to synthesizing an RTLnetlist to a gate level netlist but also to performing a number of highly sophisticated optimizations withinthe RTL representation, such as the examples listed above. ”
这是做逻辑库映射和布局布线的基础，当然这种转换后要保持原逻辑等效，FPGA的综合器干得就是这活。
