【光电集成】技术前沿：Chiplet小芯片互联技术与3D封装

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Chiplet芯片技术被《麻省理工科技评论》评为2024年十大突破性技术之一，在半导体领域取得了重大进展。这是小型模块化芯片，具有特定功能，例如可以混合搭配成完整系统的CPU或GPU。

这种类似乐高积木的方法使制造商能够灵活地以较低成本组建新芯片设计系统，并提高效率和性能。芯片实现优化的一种方法是战略性地定制技术。例如，IO和总线芯片使用可靠的传统节点，而计算芯片则采用尖端技术以实现峰值性能。内存芯片采用新兴内存技术，确保能够适应各种半导体需求。

为什么要Chiplet小芯片互联技术

在1965年的一篇研究论文中，英特尔联合创始人Gordon Moore表示，芯片上的晶体管数量大约每两年翻一番，计算能力呈指数级增长，同时成本下降。但在当今时代，鉴于单个芯片尺寸的限制，将更多晶体管安装到一个芯片上变得越来越具有挑战性。

分割大型单片系统芯片：解决摩尔定律放缓的问题

基于芯片的设计解决了过去几十年来推动半导体行业发展的摩尔定律的放缓问题。芯片制造商探索了使晶体管更小、将更多元件塞入芯片的方法，从而产生了规模可观的单片系统级芯片（SoC）设计。

手机是单片设计成功的证明，将数学函数、显示、无线通信、音频等全部集成到一个100mm²的芯片中。然而，进一步的扩展成本极高，而性能优势却微乎其微。因此，将大型、复杂的SoC分成更小的芯片，并将它们连接在一起，为特定应用构建一个系统。

因此，chiplet允许将更小的组件集成到单个封装中，从而在半导体设计中提供了更大的灵活性和可扩展性。反过来，这有助于克服与传统工艺缩放方法相关的一些物理和经济挑战。

为什么是Chiplets？

如果芯片尺寸保持不变，芯片中可以包含的功能不会增加。为了克服这种情况，chiplet提供了一个解决方案。你可以将功能分成多个较小的芯片，而不是一个大芯片。例如，如果你将一个800毫米芯片分解成四个较小的800毫米芯片，并将它们互连，可以实现相当于3200毫米芯片的芯片，有效提高整体功能，而不受单芯片尺寸限制的限制。

chiplet的另一个好处是可组合性和可重复使用性。chiplet可以快速轻松地定制和升级，从而缩短开发时间并降低成本。这种灵活性使芯片制造商能够快速应对不断变化的市场需求和新技术的进步。

一般的人工智能计算芯片可以使用高带宽的die to die芯片（即chiplet到chiplet）I/O构建，然后可以封装大量的DRAM带宽，以构建理想的LLM推理芯片。多个人工智能芯片可以封装在一起作为高端解决方案，或者只封装一个作为低成本选项。在所有这些情况下，一旦创建了最初的芯片，设计和实现成本主要在封装上。

Chiplets这个概念并不新鲜。多芯片模块已经存在了几十年。早在1995年，英特尔在奔腾Pro中结合了CPU芯片和SRAM芯片。

什么是Chiplet?

Chiplet是功能性集成线路块，通常由可重用的IP（知识产权）块组成。与将所有功能集成到单个整体芯片的传统SoC不同，基于Chiplet的设计将这些功能分割成独立的较小芯片，可以使用不同的工艺制造，然后使用先进的封装技术集成。

两种Chiplet异构集成方法：（a）芯片分割和集成，（b）芯片分区和集成。

Chiplet的发展历程

Chiplet从早期的理论探索逐步发展到如今越来越广泛的应用，成为突破摩尔定律限制、提升芯片性能的关键技术，经历了多个关键发展阶段。

概念原型。实际上，被称为摩尔定律“拯救者”的Chiplet的原始理念是与摩尔定律一同诞生的，1965 年Gordon Moore在国际电信联盟IEEE的学术年会上提交了一篇论文，在此文中他提出了带给世界深远影响的摩尔定律，同时在此文中他还指出，用较小功能构建大型系统更经济，这些功能单独包装和连接，这便是Chiplet最初的概念原型。

早期概念与雏形初现。随着集成电路和半导体封装技术的不断发展，20世纪70年代兴起了一种先进的混合集成电路技术，由多个同质或异质的较小芯片组成大芯片，被称为多芯片模组（MCM）技术，这即是Chiplet的早期概念。2010年，时任台积电研发副总裁的蒋尚义先生提出区别于传统封装的方法——通过半导体互联技术连接两颗芯片，并将其定义为先进封装。后来华为海思与台积电于2014年合作的64位Arm架构服务器处理器Hi16xx，采用了台积电异构封装工艺，被视为Chiplet技术的一种早期应用。2015年，Marvell 创始人周秀文在ISSCC 2015大会上提出Mochi（Modular Chip，模块化芯片）架构的概念，成了Chiplet的早期雏形。

快速发展。工业界从2016年左右就在逐步尝试基于Chiplet的芯片设计，AMD、Intel、英伟达等国际芯片巨头纷纷入局Chiplet，国内也有越来越多的公司在产品中应用Chiplet，Chiplet技术进入快速发展阶段。

建立互联标准。随着Chiplet的应用不断拓展，人们逐渐意识到碎片化、定制化的行业标准会降低Chiplet的设计和制造效率，限制相关的行业合作与技术创新，对其未来发展十分不利。而为了建立一个开放、可互操作的Chiplet生态系统，2022年3月，由Intel、AMD、ARM、ASE等十大行业巨头共同开发制定的开放行业互联标准UCIe（Universal Chiplet Interconnection Express）正式推出。同年12月，中国首个原生Chiplet技术标准——《小芯片接口总线技术要求》团体标准，也正式通过审定并发布。

IEEE 启动 Chiplet标准制订工作。全球各种团体标准的制订仍未能完全解决Chiplet的互联问题，因此有必要制订国际性的统一互联标准。2024年3月20日，由多名Chiplet技术专家组成的IEEE chiplet interface circuit 研究工作组通过了IEEE NesCom（IEEE新标准委员会）的立项评审和IEEE SASB（IEEE标准组织董事会）的批准，正式开始Chiplet标准的制订工作。

Chiplet小芯片互联技术——异构集成

为支持Chiplet异构集成，出现了几种先进的小芯片互联与封装技术：

1. 有机基板上的2D Chiplet集成：

这种方法将Chiplet并排放置在有机基板上。AMD的EPYC处理器使用了这种技术。

2. 有机基板上的2.1D Chiplet集成：这种方法在有机基板上添加薄膜层，以提高互连密度。新光电气的i-THOP（集成薄膜高密度有机封装）是这种技术的一个例子。

新光电气在有机基板上的2.1D Chiplet异构集成。

硅中介层上的2.5D Chiplet集成

这种技术使用带有硅通孔（TSV）的无源硅中介层来连接Chiplet。台积电的晶圆级封装（CoWoS）是一个突出的例子。

在无源TSV中介层上的2.5D（CoWoS-2） Chiplet异构集成。

3D Chiplet集成

这种方法使用带有TSV的有源中介层垂直堆叠Chiplet。英特尔的Foveros技术是这种技术的主要代表。

带硅桥的Chiplet集成

这种方法在有机基板中嵌入硅桥来连接Chiplet。英特尔的EMIB（嵌入式多芯片互连桥）使用了这种方法。

英特尔在带硅桥的有机基板上的Chiplet异构集成（Agilex FPGA）。

英特尔的Lakefield处理器：

英特尔的Lakefield移动处理器使用Foveros 3D封装技术垂直堆叠Chiplet。这种方法可以在适合移动设备的紧凑形态下实现高性能。

使用Foveros技术的英特尔Lakefield移动处理器。

封装叠加（PoP） Chiplet集成

这种技术垂直叠加封装，通常结合逻辑和存储Chiplet。苹果的A系列处理器使用这种方法，结合台积电的InFO（集成扇出）技术。

图8：苹果iPhone的PoP InFO Chiplet异构集成。

Chiplet的优势

相较于传统芯片技术，Chiplet具有多个显著的优点，这些优点使其在芯片设计和制造领域展现出独特优势。

灵活性高，可扩展性强。Chiplet把单芯片设计变成了多芯片模块化设计。它将一块大裸片拆分成多个die进行设计、制造和测试，设计出的die再根据不同需求进行组合，类似于搭建乐高积木，通过一组小裸片混搭成一个“类乐高”的组件，能设计出满足各种功能或体积要求的芯片，这种灵活性使得Chiplet在应对复杂数据处理和计算任务时更具优势。

良品率高，损耗较低。相较于SoC，Chiplet的尺寸要小得多，有的甚至可以达到一粒沙子的大小，因此芯片制造过程中当晶圆缺陷密度一定时，这种小型化的特点使得Chiplet产生缺陷的概率大大降低，提高良率的同时减少了成本损耗。

提升性能。相较于SoC的单一工艺和材质设计，Chiplet支持将不同功能不同材质不同制程的die集成在一起，各家优势结合，实现芯片性能的翻倍。

降低设计复杂度与研发成本。相较于SoC的整体集成和SIP的整体封装，Chiplet的单元设计还可避免许多重复设计。一旦某个芯片单元设计完成并通过验证，便可在多个芯片系统中进行组装复用，降低了研发成本，缩短了产品上市周期，利于后续产品迭代。

2.5D中介层技术

芯片能否成功跟上摩尔定律，很大程度上取决于芯片在一个封装内能被放置得有多近，以确保它们之间快速、高带宽的电连接。在2.5D集成中，芯片通过硅、有机聚合物、玻璃或层压板等公共基板连接。

硅中介层是一种成熟的高性能应用技术，具有最精细的间距和良好的热电性能，但它们的成本和复杂性也更高。因此，有机基板作为替代方案得到了研究和优化。Imec提供的硅“桥”和超精细再分布层（RDL）互连技术是两种替代方案。

3D片上系统：混合键合实现亚微米间距

某些应用（如高性能计算）可能需要高性能、更小的外形尺寸或更高级别的系统集成，更倾向于采用完整的3D方法。晶圆到晶圆混合键合是集成3D-SoC到微米互连密度级别的关键技术。Imec的专有方法使用SiCN作为键合电介质，将互连间距缩小到700nm，未来可能达到400nm和200nm。

微凸块与混合键合：不同互连技术的比较

对于2.5D技术，使用小焊料凸块将芯片放置在中介层顶部，从而建立电气和机械连接。工业上的微凸块间距通常达到50µm到30µm之间。Imec正在研究如何将间距减小到10µm甚至5µm。

与2.5D中使用的微凸块相比，3D堆叠中的混合键合产生的间距要小得多。那么，是否可以在任何地方使用混合键合呢？

事实上，在芯片到晶圆的方法（基于硅）中，芯片可以键合到硅中介层，间距达到几微米。不是200nm，因为目前最好的芯片到晶圆放置精度接近250nm，而前沿的晶圆到晶圆键合可以降低到100nm的叠加精度。键合设备和相关工艺的改进预计将进一步将这些数字降低50%。不过，混合键合涉及额外的加工步骤，例如表面活化和对准，这可能会影响制造成本。

晶圆对晶圆键合、芯片对晶圆键合和微凸块将在成本、间距、兼容性和互操作性之间共存。在2.5D中，芯片通常来自不同的供应商，并且已经经过了一系列测试和操作。微凸块将成为首选，因为它们提供了一种不需要表面处理的标准化方法。此外，对于有机RDL，微凸块仍然是首选，因为有机聚合物在加热时会膨胀得更多，并且无法充分平坦化。

近年来，3.5D封装技术逐渐走向前台，作为2.5D和3D-IC技术之间的一种折中方案，3.5D封装结合了两者的优势，并在解决散热、噪声和信号完整性等方面展现出了独特的能力，技术的提出和应用标志着半导体封装领域的重大突破。

3.5D 封装的优势与挑战

3.5D封装通过将逻辑芯片堆叠，并将它们分别粘合到其他组件共享的基板上，创造了一种新的架构。

这种架构的优势在于它能够有效解决热管理和噪声问题，同时提供了在高速设计中增加更多SRAM的可能性。

SRAM作为处理器缓存的首选，虽然其扩展性已经遇到瓶颈，但通过3.5D封装技术，可以在不增加物理面积的情况下实现更多内存的集成。

此外，3.5D封装还能够缩短信号传输的距离，大幅提升处理速度，这对于人工智能和大数据应用尤为重要。

3.5D封装并非没有挑战。

完全集成的3D-IC在处理物理效应时遇到的困难依然存在，尤其是在散热和电源噪声方面。

随着芯片元件的增加，动态热梯度和电磁干扰问题也变得更加复杂。3.5D封装虽然在一定程度上缓解了这些问题，但在更复杂的应用场景中，仍然需要进一步的优化和改进。

3.5D封装技术在市场上的应用逐渐增多，特别是在高性能计算和数据中心领域，市场对高性能芯片的需求促使了3.5D封装的广泛应用，特别是在散热和信号完整性方面。

这种封装技术通过硅中介层实现芯片之间的高效连接，同时也提供了较好的散热性能，使其成为当前市场上性能最优的选择之一。除了数据中心，3.5D封装还被广泛应用于AI/ML领域。

随着大语言模型和深度学习的需求不断增长，处理器对高速内存的需求也随之增加。通过3.5D封装，可以在有限的物理空间内实现更高的计算能力和更低的功耗，从而满足这些领域的需求。

3.5D封装的应用并不仅限于高性能计算和AI/ML领域。随着工艺技术的进步，这种封装技术将在更多的消费电子、通信设备以及物联网设备中得到应用。这将进一步推动市场对3.5D封装技术的需求，促使其成为主流封装技术之一。

互连技术的未来方向：挑战与机遇

随着规模化技术变得越来越复杂，设计和加工成本也越来越高，对于规模较小的应用来说，在最先进的技术节点中开发专用SoC变得越来越具有挑战性。将功能和技术节点分成不同的芯片组更具成本效益，并且比采用尖端工艺技术的巨型芯片具有空间和性能优势。

模块化方法可以解决多芯片封装的复杂性和成本问题，但这种模式转变带来了特定的技术挑战。尺寸只是挑战之一。芯片研究的很大一部分致力于缩小互连和/或探索将各个部件组合在一起的不同概念。将芯片堆叠在一起时，散热问题和电力输送变得至关重要。最后，需要进一步的标准化工作，以确保不同芯片之间的兼容性和通信。

技术演进与未来展望

3.5D封装技术的发展离不开工艺技术的不断进步。

近年来，随着晶圆工艺的进步，芯片堆叠技术得到了极大的提升。例如，三星代工业务开发副总裁Taejoong Song在最近的活动中展示了3.5D配置的路线图，计划在未来几年内实现2nm和4nm芯片的堆叠。

这一技术的发展将进一步提升3.5D封装的性能和集成度，使其能够满足更高性能和更复杂的应用需求。

混合键合技术的应用也为3.5D封装带来了新的可能性。通过混合键合，可以在更小的空间内实现更多的连接，从而提高封装的密度和性能。

这一技术的应用不仅能够提升芯片的集成度，还能够降低功耗和热量，使其在更广泛的应用场景中得到应用。

3.5D封装技术的发展仍面临一些挑战，工艺的复杂性和制造成本是制约其大规模应用的主要因素。虽然当前的技术已经能够实现较为稳定的3.5D封装，但在大规模生产和应用中，仍需要进一步降低成本和提高良率。

其次，3.5D封装的可靠性和长期稳定性也需要进一步验证，特别是在高温和高压环境下的应用场景中。

3.5D封装技术的推广和应用还需要产业链各环节的密切合作。

EDA工具、封装材料和测试设备的标准化是实现大规模应用的关键。IC设计师需要同时考虑热管理、信号完整性和电源完整性，这需要EDA工具的支持以及设计流程的优化。

此外，工艺/装配设计套件的标准化也是关键因素，这将帮助代工厂和OSAT（封测厂）更好地合作，推动3.5D封装技术的应用。产业链各环节的合作对于3.5D封装技术的推广至关重要。

从设计到制造，再到测试和封装，各个环节都需要密切配合，以确保3.5D封装技术的顺利实现。只有在整个产业链形成紧密合作的生态系统，3.5D封装技术才能真正实现大规模应用，并推动整个半导体行业的技术进步。

Technology frontier: Chiplet interconnection technology and 3D packaging

Named one of the top 10 breakthrough technologies of 2024 by MIT Technology Review, chiplet chip technology has made significant progress in the field of semiconductors. These are small modular chips with specific features, such as CPUs or GPUs that can be mixed and matched into a complete system.

This Lego-like approach gives manufacturers the flexibility to assemble new chip design systems at a lower cost, with improved efficiency and performance. One way to optimize silicon is to strategically tailor the technology. For example, IO and bus chips use reliable legacy nodes, while compute chips use cutting-edge technology to achieve peak performance. Memory chips incorporate emerging memory technologies to ensure that they can be adapted to a wide range of semiconductor needs.

Why Chiplet interconnect technology

In a 1965 research paper, Intel co-founder Gordon Moore said that the number of transistors on chips was doubling about every two years, and that computing power was growing exponentially while costs were falling. But in this day and age, it is becoming increasingly challenging to fit more transistors onto a single chip, given the limitations of the size of a single chip.

Splitting large monolithic SoCs: Solving the problem of Moore's Law slowing down

Chip-based design solves the slowdown of Moore's Law, which has driven the semiconductor industry over the past few decades. Chipmakers have explored ways to make transistors smaller and fit more components into the chip, resulting in sizable monolithic system-on-chip (SoC) designs.

The mobile phone is a proof of the success of a monolithic design, integrating mathematical functions, displays, wireless communications, audio, etc. into a single 100mm² chip. However, further scaling is extremely costly, and the performance benefits are minimal. So, break up large, complex SoCs into smaller chips and connect them together to build a system for a specific application.

As a result, chiplets allow smaller components to be integrated into a single package, providing greater flexibility and scalability in semiconductor designs. This, in turn, helps to overcome some of the physical and economic challenges associated with traditional process scaling methods.

Why Chiplets?

If the chip size remains the same, there is no increase in the functions that can be included in the chip. To overcome this situation, chiplets provide a solution. You can split the functionality into multiple smaller chips instead of one large chip. For example, if you break down an 800mm chip into four smaller 800mm chips and interconnect them, you can achieve a chip equivalent to a 3200mm chip, effectively improving the overall functionality without being limited by the size of a single chip.

Another benefit of chiplets is composability and reusability. Chiplets can be quickly and easily customized and upgraded, reducing development time and costs. This flexibility allows chipmakers to respond quickly to changing market demands and advances in new technologies.

General AI computing chips can be built using high-bandwidth die-to-die chips (i.e., chiplet-to-chiplet) I/O, and then a large amount of DRAM bandwidth can be encapsulated to build an ideal LLM inference chip. Multiple AI chips can be packaged together as a high-end solution, or just one as a low-cost option. In all of these cases, once the initial chip has been created, the design and implementation costs are primarily in the package.

The concept of chiplets is not new. Multi-chip modules have been around for decades. Back in 1995, Intel combined CPU chips and SRAM chips in the Pentium Pro.

What is a Chiplet?

Chiplets are functionally integrated circuit blocks, typically consisting of reusable IP (intellectual property) blocks. Unlike traditional SoCs, which integrate all functions into a single monolithic chip, chiplet-based designs split these functions into separate, smaller chips that can be fabricated using different processes and then integrated using advanced packaging techniques.

There are two methods of heterogeneous integration of chiplets: (a) chip segmentation and integration, and (b) chip partitioning and integration.

The history of chiplets

Chiplet has gradually developed from the early theoretical exploration to more and more extensive applications today, and has become a key technology to break through the limitations of Moore's Law and improve the performance of chips, and has gone through several key stages of development.

Conceptual prototypes. In 1965, Gordon Moore presented a paper at the annual meeting of the International Telecommunication Union (IEEE), in which he proposed Moore's Law, which had a profound impact on the world, and in which he also pointed out that it is more economical to build large systems with smaller functions, which are packaged and connected separately, which was the original conceptual prototype of Chiplet.

Early concepts and prototypes emerged. With the continuous development of integrated circuits and semiconductor packaging technology, an advanced hybrid integrated circuit technology emerged in the 70s of the 20th century, which consists of a number of homogeneous or heterogeneous smaller chips to form large chips, known as multi-chip module (MCM) technology, which is the early concept of chiplet. In 2010, Mr. Jiang Shangyi, then vice president of R&D at TSMC, proposed a different method from traditional packaging - connecting two chips through semiconductor interconnect technology, and defined it as advanced packaging. Later, the 64-bit Arm-based server processor Hi16xx, which Huawei HiSilicon and TSMC collaborated on in 2014, adopted TSMC's heterogeneous packaging process and was regarded as an early application of Chiplet technology. In 2015, Marvell founder Xiuwen Zhou proposed the concept of Mochi (Modular Chip) architecture at the ISSCC 2015 conference, which became the early prototype of chiplets.

Rapid development. Since around 2016, the industry has been gradually trying to design chips based on Chiplet, and international chip giants such as AMD, Intel, and Nvidia have entered Chiplet, and more and more companies in China have applied Chiplet in their products, and Chiplet technology has entered a stage of rapid development.

Establish connectivity standards. With the continuous expansion of the application of chiplets, people gradually realize that fragmented and customized industry standards will reduce the design and manufacturing efficiency of chiplets, limit related industry cooperation and technological innovation, and be very detrimental to their future development. In order to build an open and interoperable chiplet ecosystem, in March 2022, UCIe (Universal Chiplet Interconnection Express), an open industry interconnection standard jointly developed and formulated by ten industry giants including Intel, AMD, ARM, AND ASE, was officially launched. In December of the same year, China's first native chiplet technology standard, the group standard of "Technical Requirements for Chiplet Interface Bus", was also officially approved and released.

IEEE initiates work on chiplet standards. The development of various group standards around the world has not yet completely solved the interconnection problem of chiplets, so it is necessary to develop an international unified interconnection standard. On March 20, 2024, the IEEE chiplet interface circuit research working group, composed of several chiplet technical experts, passed the project review of IEEE NesCom (IEEE New Standards Committee) and the approval of IEEE SASB (IEEE Standards Organization Board of Directors), and officially began the development of chiplet standards.

Chiplet interconnection technology - heterogeneous integration

To support the heterogeneous integration of chiplets, several advanced chiplet interconnect and packaging technologies have emerged:

1. 2D Chiplet Integration on Organic Substrates:

In this method, the chiplets are placed side-by-side on an organic substrate. AMD's EPYC processors use this technology.

2. 2.1D Chiplet Integration on Organic Substrates: This method adds a thin film layer to the organic substrate to increase the interconnect density. Shin Ko Electric's i-THOP (Integrated Thin Film High Density Organic Package) is an example of this technology.

Xinguang Electric's heterogeneous integration of 2.1D chiplets on organic substrates.

2.5D chiplet integration on silicon interposer

This technology uses a passive silicon interposer with through-silicon vias (TSVs) to connect chiplets. TSMC's Wafer Level Packaging (CoWoS) is a prominent example.

Heterogeneous integration of 2.5D (CoWoS-2) chiplets on a passive TSV interposer.

3D chiplet integration

This method uses an active interposer with TSV to stack chiplets vertically. Intel's Foveros technology is the main exponent of this technology.

带硅桥的Chiplet集成这

A method embeds a silicon bridge in an organic substrate to connect chiplets. Intel's EMIB (Embedded Multi-Chip Interconnect Bridge) uses this approach.

Intel's heterogeneous integration of chiplets on organic substrates with silicon bridges (Agilex FPGAs).

Intel's Lakefield Processors:

Intel's Lakefield mobile processors use Foveros 3D packaging technology to vertically stack chiplets. This approach enables high performance in a compact, mobile-friendly form factor.

Intel Lakefield mobile processors using Foveros technology.

封装叠加（PoP） Chiplet集成

This technology is vertically stacked and packaged, typically combining logic and memory chiplets. Apple's A-series processors use this method, combined with TSMC's InFO (Integrated Fan-Out) technology.

图8：苹果iPhone的PoP InFO Chiplet异构集成。

Advantages of Chiplets:

Chiplets have several significant advantages over traditional chip technology, which make them unique in the field of chip design and manufacturing.

High flexibility and scalability. Chiplets turn a single-chip design into a multi-chip modular design. It splits a large die into multiple dies for design, manufacturing and testing, and then combines the designed dies according to different needs, similar to building Lego bricks, through a group of small bare chips mixed and matched into a "Lego-like" component, which can design chips that meet various functional or volume requirements, and this flexibility makes chiplets more advantageous when dealing with complex data processing and computing tasks.

The yield rate is high and the loss is low. Compared with SoC, the size of chiplets is much smaller, and some can even reach the size of a grain of sand, so when the wafer defect density is certain in the chip manufacturing process, this miniaturization feature greatly reduces the probability of chiplet defects, improves the yield and reduces the cost loss.

Boost performance. Compared with the single process and material design of the SoC, the chiplet supports the integration of dies with different functions, materials and processes, and the advantages of each are combined to double the performance of the chip.

Reduce design complexity and R&D costs. Compared to the overall integration of the SoC and the overall packaging of the SIP, the cell design of the chiplet also avoids many duplicate designs. Once a chip unit is designed and verified, it can be assembled and reused in multiple chip systems, reducing R&D costs, shortening the time-to-market, and facilitating subsequent product iterations.

2.5D interposer technology

The success of a chip to keep up with Moore's Law depends largely on how close the chip can be placed within a package to ensure a fast, high-bandwidth electrical connection between them. In 2.5D integration, the chips are connected via a common substrate such as silicon, organic polymer, glass, or laminate.

Silicon interposers are a proven, high-performance application technology with the finest pitch and good thermoelectric properties, but they are also more expensive and complex. Therefore, organic substrates have been studied and optimized as alternatives. The silicon "bridge" and ultra-fine redistribution layer (RDL) interconnect technologies offered by Imec are two alternatives.

3D system-on-chip: Hybrid bonding for sub-micron pitch

Some applications, such as high-performance computing, may require high performance, a smaller form factor, or a higher level of system integration, preferring a full 3D approach. Wafer-to-wafer hybrid bonding is a key technology for integrating 3D-SoCs into micron interconnect density levels. Imec's proprietary method uses SiCN as a bonding dielectric to reduce the interconnect pitch to 700nm, with the potential to reach 400nm and 200nm in the future.

Microbump vs. Hybrid Bonding: A Comparison of Different Interconnect Technologies

For 2.5D technology, a small solder bump is used to place the chip on top of the interposer, creating an electrical and mechanical connection. Micro-bump pitches in industry typically range from 50 μm to 30 μm. Imec is working on how to reduce the pitch to 10 μm or even 5 μm.

Compared to the microbumps used in 2.5D, hybrid bonding in 3D stacking results in much smaller spacing. So, is it possible to use hybrid bonding anywhere?

In fact, in a chip-to-wafer approach (silicon-based), chips can be bonded to a silicon interposer with pitches up to a few microns. Not 200nm, because the best chip-to-wafer placement accuracy is close to 250nm at the moment, while cutting-edge wafer-to-wafer bonding can be reduced to 100nm stacking accuracy. Improvements in bonding equipment and related processes are expected to further reduce these numbers by a further 50%. However, hybrid bonding involves additional processing steps, such as surface activation and alignment, which can impact manufacturing costs.

Wafer-to-wafer bonding, chip-to-wafer bonding, and micro-bumping will coexist between cost, pitch, compatibility, and interoperability. In 2.5D, the chips are usually from different suppliers and have undergone a series of tests and operations. Microbumps will be preferred as they provide a standardized method that does not require surface treatment. In addition, for organic RDL, micro-bumps are still preferred because organic polymers swell more when heated and do not flatten sufficiently.

In recent years, 3.5D packaging technology has gradually come to the forefront, as a compromise between 2.5D and 3D-IC technology, 3.5D packaging combines the advantages of both, and shows a unique ability to solve heat dissipation, noise and signal integrity, etc., and the proposal and application of technology marks a major breakthrough in the field of semiconductor packaging.

Advantages and challenges of 3.5D packaging

3.5D packaging creates a new architecture by stacking logic chips and bonding them separately to a substrate shared by other components.

The advantage of this architecture is that it effectively solves thermal management and noise problems, while providing the possibility to add more SRAM to high-speed designs.

SRAM is the first choice for processor cache, and although its scalability has reached a bottleneck, with 3.5D packaging technology, more memory can be integrated without increasing the physical area.

In addition, the 3.5D package can also shorten the distance of signal transmission and greatly increase the processing speed, which is especially important for artificial intelligence and big data applications.

3.5D packaging is not without its challenges.

Difficulties in dealing with physical effects with fully integrated 3D-ICs remain, especially in terms of heat dissipation and power supply noise.

As the number of chip components increases, the problems of dynamic thermal gradients and electromagnetic interference become more complex. Although 3.5D packaging alleviates these problems to a certain extent, it still needs further optimization and improvement in more complex application scenarios.

The application of 3.5D packaging technology in the market is gradually increasing, especially in the field of high-performance computing and data centers, and the market demand for high-performance chips has prompted the widespread application of 3.5D packaging, especially in heat dissipation and signal integrity.

This packaging technology enables efficient connections between chips through a silicon interposer, while also providing good heat dissipation, making it one of the best performing options on the market today. In addition to data centers, 3.5D packaging is also widely used in AI/ML fields.

As the demand for large language models and deep learning continues to grow, so does the need for high-speed memory for processors. With 3.5D packaging, higher computing power and lower power consumption can be achieved in a limited physical space to meet the needs of these fields.

The application of 3.5D packaging is not limited to high-performance computing and AI/ML. As process technology advances, this packaging technology will be used in more consumer electronics, communication devices, and IoT devices. This will further drive the market demand for 3.5D packaging technology, making it one of the mainstream packaging technologies.

The Future of Interconnect: Challenges and Opportunities

As scaled technologies become more complex and expensive to design and fabricate, it becomes increasingly challenging to develop dedicated SoCs in state-of-the-art technology nodes for smaller applications. Separating functional and technical nodes into different chipsets is more cost-effective and offers space and performance advantages over giant chips with cutting-edge process technology.

A modular approach can address the complexity and cost of multi-chip packaging, but this paradigm shift presents specific technical challenges. Size is just one of the challenges. A large part of chip research is dedicated to shrinking interconnects and/or exploring different concepts that put individual parts together. When stacking chips on top of each other, heat dissipation issues and power delivery become critical. Finally, further standardization work is needed to ensure compatibility and communication between different chips.

Technology Evolution and Future Prospects

The development of 3.5D packaging technology is inseparable from the continuous progress of process technology.

In recent years, with the advancement of wafer technology, chip stacking technology has been greatly improved. For example, Taejoong Song, VP of Foundry Business Development at Samsung, presented a roadmap for 3.5D configurations at a recent event, with plans to enable the stacking of 2nm and 4nm chips in the next few years.

The development of this technology will further enhance the performance and integration of 3.5D packaging, enabling it to meet the needs of higher performance and more complex applications.

The application of hybrid bonding technology also brings new possibilities for 3.5D packaging. With hybrid bonding, more connections can be made in a smaller space, increasing the density and performance of the package.

The application of this technology can not only improve the integration of chips, but also reduce power consumption and heat, making it suitable for a wider range of application scenarios.

The development of 3.5D packaging technology still faces some challenges, and the complexity of the process and the manufacturing cost are the main factors restricting its large-scale application. While current technologies have been able to achieve relatively stable 3.5D packaging, there is still a need to further reduce costs and improve yields in mass production and applications.

Secondly, the reliability and long-term stability of the 3.5D package also need to be further verified, especially in the application scenarios in high-temperature and high-pressure environments.

The promotion and application of 3.5D packaging technology also require close cooperation among all links in the industrial chain.

Standardization of EDA tools, packaging materials, and test equipment is key to achieving large-scale adoption. IC designers need to consider thermal management, signal integrity, and power integrity at the same time, which requires the support of EDA tools and the optimization of the design flow.

In addition, the standardization of process/assembly design kits is also a key factor, which will help foundries and OSATs (assembly and test plants) to better cooperate and promote the adoption of 3.5D packaging technology. The cooperation of all links in the industrial chain is crucial to the promotion of 3.5D packaging technology.

From design to manufacturing, to testing and packaging, all aspects need to work closely together to ensure the smooth implementation of 3.5D packaging technology. Only by forming a close ecosystem of cooperation across the entire industry chain can 3.5D packaging technology truly achieve large-scale application and promote the technological progress of the entire semiconductor industry.

来源：AIOT大数据