《基于“矿板”低成本学习FPGA》使用ILA内部逻辑分析仪分析LED工程的信号

module led(    input sys_clk,      //system clock 50MHZ on board    input rst_n,        //reset low active    output reg[2:0] led    //LED use of control the LED signal on board); 
reg [31:0] timer;
//==============================//cle counter : from 0 to 4 sec//==============================always @(posedge sys_clk or negedge rst_n)    begin        if(~rst_n)            timer <= 32'd0;                 //when the reset signal valid,time counter clearing        else if(timer == 32'd149_999_999)   //4 seconds count(50M * 4 - 1 = 199_999_999)            timer <= 32'd0;                 //count done,clearing the time counter        else            timer <= timer + 1'b1;          //timer counter = timer counter + 1     end//==============================//LED control//==============================always @(posedge sys_clk or negedge rst_n)    begin        if(~rst_n)            led <= 3'b111;        else if(timer == 32'd49_999_999)            led <= 3'b011;        else if(timer == 32'd99_999_999)            led <= 3'b110;        else if(timer == 32'd149_999_999)            led <= 3'b101;    end        
ila_0 u_ila(    .clk(sys_clk),    .probe0(rst_n),    .probe1(led[0]),    .probe2(led[1]),    .probe3(led[2])    );    endmodule

module led(    input sys_clk,      //system clock 50MHZ on board    input rst_n,        //reset low active    output reg[2:0] led    //LED use of control the LED signal on board); 
reg [31:0] timer;
//==============================//cle counter : from 0 to 4 sec//==============================always @(posedge sys_clk or negedge rst_n)    begin        if(~rst_n)            timer <= 32'd0;                 //when the reset signal valid,time counter clearing        else if(timer == 32'd15)   //4 seconds count(50M * 4 - 1 = 199_999_999)            timer <= 32'd0;                 //count done,clearing the time counter        else            timer <= timer + 1'b1;          //timer counter = timer counter + 1     end//==============================//LED control//==============================always @(posedge sys_clk or negedge rst_n)    begin        if(~rst_n)            led <= 3'b111;        else if(timer == 32'd5)            led <= 3'b011;        else if(timer == 32'd10)            led <= 3'b110;        else if(timer == 32'd15)            led <= 3'b101;    end        
ila_0 u_ila(    .clk(sys_clk),    .probe0(rst_n),    .probe1(led[0]),    .probe2(led[1]),    .probe3(led[2])    );    endmodule