hal库超好用？来看看以太网的bug

鱼鹰谈单片机 2024-07-09 08:40 970浏览 0评论 0点赞

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stm32H7 hal 库里面的以太网代码，坑了鱼鹰很多次（不知道最新版是否已经修复了这些bug），这里分享一篇网上的文章，因为鱼鹰也遇到过，靠它解决了其中一个编译优化问题，在此感谢作者。不过hal库里面远不止这些bug（主要是项目环境太复杂了，一般情况很难触发），还有更多bug没在此文章描述，而鱼鹰碰到了......

问题

最近在调试STM32H750+LAN8720，搞了大半天终于移植好LwIP了，ping也能ping通，TCP测试也成功。本来以为ST的HAL库终于省心了，结果我将编译优化开到最大…

…直接ping都ping不通了。后来发现HAL库有很大问题。(果然HAL库还是不省心，生成的代码只有初始化能用)

后面发现，HAL库有两个隐患:

1、对描述符的处理有问题

2、因为单片机是Cortex-M7，有Cache和单片机会乱序执行和乱序访问内存，乱序访问对发送/接收描述符操作有很大的隐患

后面对这些问题详细描述

原因

问题1 HAL库的隐患1 处理方式

我感觉HAL库处理数据描述符的方式似乎很有问题，例如

SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);//居然在这里将描述符权限给了ETH
if(dmarxdesclist->ItMode != 0U){  SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);//描述符都给了ETH居然还要修改}

这是stm32h7xx_hal_eth.c中

HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)

的一段代码，描述符的OWN在我看来应该是最后才设置的，因为它是标记描述符当前是ETH所有还是用户(CPU等其他玩意)所有，但从这段代码看来，它把描述符归还ETH后居然还对这个描述符进行修改，这是要趁ETH不注意吗，如果真是这样，ETH还真的能正常运行！但是这无疑是一个安全隐患。一个直接体现就是我把编译优化打开(-O3)以太网通信就出问题了。

并且这种操作在HAL库里随处可见，简直恐怖如斯

估摸着ST的人以为写入ETH->DMACRDTPR或者ETH->DMACTDTPR(用于告诉ETH描述符有更新)描述符才会生效，但我看了文档的描述，如果应用程序能一直更新描述符，即使不写入这个寄存器，ETH还是会接着发送，即描述符的OWN位的设置为1代表着描述符归ETH所有，送出去的描述符泼出去的水，用户不应该再进行修改，直到OWN被ETH清零。那ETH->DMACRDTPR或者ETH->DMACTDTPR的用处是什么呢？为了减少ETH对总线的占用，如果ETH检测不到有效的描述符(OWN都为0)，ETH将不再访问内存，所以需要一个机制来告诉ETH描述符有更新，该干活了。

而这个机制就是写入ETH->DMACRDTPR(接收描述符)或者ETH->DMACTDTPR(发送描述符)，这两个寄存器除了标记最后一个描述符的地址，还用于告诉ETH描述符有更新。

问题2 HAL库的隐患2 没有处理Cortex-M7的乱序访问和Cache的问题

正常来说，CPU的乱序执行是不会影响外设操作的。因为外设寄存器的内存类型默认为Device(还要一个类似的属性为Strongly-ordered)，这意味着乱序执行无论在怎么乱，它都会保证对这些内存正确的顺序(在代码中的执行顺序)访问。

但巧了，描述符的存放位置不在这些内存区域，它只能放在D2域的SRAM中(ETH的手只能够着这些地方)，而且这些SRAM的内存类型默认为Normal，而为了效率，CPU会对这些区域的内存乱序访问(这样关键的OWN位可能提前也可能延后被写入)，这肯定不是我们希望的。

对于开启了Cache的情况，这将变得更加复杂，可能写入的数据都没有实实在在的写入内存中。

解决方法

对于问题1，对描述符操作的代码没多少，我就自己手动修改了stm32h7xx_hal_eth.c中的相关代码(修改过的部分在后面放出)，保证代码的顺序是没问题的。主要修改OWN相关的和ETH->DMACRDTPR和ETH->DMACTDTPR相关的。

对于问题2，我是这么处理的：

配置MPU，将描述符，数据缓存所在的内存区域配置为不缓冲(Buffer)，不缓存(Cache)，TEX配置为LEVEL1(0x01)，这样这些内存就配置为了Normal，但不再受Cache的影响(这保证了一个性能的平衡，因为对于CortexM7,CleanCache操作步骤太多，虽然就调用了一个内联的函数，但其中是写一次寄存器Clean一个Cache行，整个Cache需要512次写操作还有其他相关的计算，还不如不Cache这些地方的内存，而使用Normal属性能加快内存访问速度（它似乎能把多个连续单字节的访问打包成32Bit的访问，应该是乱序访问的功劳，这个特性是我调试SDRAM测试它的速度时发现的，即使没有使能Cache，配置成Normal的访问速度比Device要快）)

在设置/清零OWN操作的前后加入__DMB()内存隔离指令(要大写的，自带编译隔离，防止这个指令被编译器重排，没想到吧，编译器也会把你的指令打乱)

LwIP的版本为2.1.0

修改完之后，单片机端使用socket API创建的tcp服务器，单向传输10MB/s，相当于80Mbps带宽，离物理能达到的100Mbps还差一点，但CPU占用率已经达到了80，90多(TCP应该比较消耗性能吧)，估计协议和性能的损耗比较大。

修改的代码

只需要修改stm32h7xx_hal_eth.c的代码

发送的修改

发送相关的有三个函数被修改


static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode){  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;  uint32_t descidx = dmatxdesclist->CurTxDesc;  uint32_t firstdescidx = dmatxdesclist->CurTxDesc;  uint32_t descnbr = 0, idx;  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
  ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;  uint32_t           bd_count = 0;
  /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */  if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))  {    return HAL_ETH_ERROR_BUSY;  }
  /***************************************************************************/  /*****************    Context descriptor configuration (Optional) **********/  /***************************************************************************/  /* If VLAN tag is enabled for this packet */  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)  {    /* Set vlan tag value */    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);    /* Set vlan tag valid bit */    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);    /* Set the descriptor as the vlan input source */    SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
    /* if inner VLAN is enabled */    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)    {      /* Set inner vlan tag value */      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));      /* Set inner vlan tag valid bit */      SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
      /* Set Vlan Tag control */      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
      /* Set the descriptor as the inner vlan input source */      SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);      /* Enable double VLAN processing */      SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);    }  }
  /* if tcp segmentation is enabled for this packet */  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)  {    /* Set MSS value */    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);    /* Set MSS valid bit */    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);  }
  if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))  {    /* Set as context descriptor */    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);    /* Set own bit */    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);    /* Increment current tx descriptor index */    INCR_TX_DESC_INDEX(descidx, 1U);    /* Get current descriptor address */    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
    descnbr += 1U;
    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */    if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)    {      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];      /* Clear own bit */      CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
      return HAL_ETH_ERROR_BUSY;    }  }
  /***************************************************************************/  /*****************    Normal descriptors configuration     *****************/  /***************************************************************************/
  descnbr += 1U;
  /* Set header or buffer 1 address */  WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);  /* Set header or buffer 1 Length */  MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
  if(txbuffer->next != NULL)  {    txbuffer = txbuffer->next;    /* Set buffer 2 address */    WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);    /* Set buffer 2 Length */    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));  }  else  {    WRITE_REG(dmatxdesc->DESC1, 0x0);    /* Set buffer 2 Length */    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);  }
  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)  {    /* Set TCP Header length */    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));    /* Set TCP payload length */    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);    /* Set TCP Segmentation Enabled bit */    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);  }  else  {    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)    {      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);    }
    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)    {      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);    }  }
  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)  {    /* Set Vlan Tag control */    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);  }
  /* Mark it as First Descriptor */  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);  /* Mark it as NORMAL descriptor */  CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
  /* If source address insertion/replacement is enabled for this packet */  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)  {    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);  }
  /* only if the packet is split into more than one descriptors > 1 */  while (txbuffer->next != NULL)  {    /* Clear the LD bit of previous descriptor */    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);    __DMB();//修改!!    /* set OWN bit of Last descriptor */    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);    __DMB();//修改!!
    /* Increment current tx descriptor index */    INCR_TX_DESC_INDEX(descidx, 1U);    /* Get current descriptor address */    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
    /* Clear the FD bit of new Descriptor */    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */    if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))    {      descidx = firstdescidx;      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
      /* clear previous desc own bit */      for(idx = 0; idx < descnbr; idx ++)      {        __DMB();//修改!!        CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);        __DMB();//修改!!
        /* Increment current tx descriptor index */        INCR_TX_DESC_INDEX(descidx, 1U);        /* Get current descriptor address */        dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];      }
      return HAL_ETH_ERROR_BUSY;    }
    descnbr += 1U;
    /* Get the next Tx buffer in the list */    txbuffer = txbuffer->next;
    /* Set header or buffer 1 address */    WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);    /* Set header or buffer 1 Length */    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
    if (txbuffer->next != NULL)    {      /* Get the next Tx buffer in the list */      txbuffer = txbuffer->next;      /* Set buffer 2 address */      WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);      /* Set buffer 2 Length */      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));    }    else    {      WRITE_REG(dmatxdesc->DESC1, 0x0);      /* Set buffer 2 Length */      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);    }
    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)    {      /* Set TCP payload length */      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);      /* Set TCP Segmentation Enabled bit */      SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);    }    else    {      /* Set the packet length */      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
      if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)      {        /* Checksum Insertion Control */        MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);      }    }
    bd_count += 1U;
    /* Mark it as NORMAL descriptor */    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);      }
  if(ItMode != ((uint32_t)RESET))  {    /* Set Interrupt on completion bit */    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);  }  else  {    /* Clear Interrupt on completion bit */    CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);  }
  /* Mark it as LAST descriptor */  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
  __DMB();//修改!!
  /* Set Own bit For End Desc */  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);    /* Save the current packet address to expose it to the application */  dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
  dmatxdesclist->CurTxDesc = descidx;
  /* disable the interrupt */  //__disable_irq();  //我最看不惯的就是关中断!!  //dmatxdesclist->BuffersInUse += bd_count + 1U;
  /* Enable interrupts back */  //__enable_irq();

  /* Return function status */  return HAL_ETH_ERROR_NONE;}

HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout){  uint32_t tickstart;  const ETH_DMADescTypeDef *dmatxdesc;
  if(pTxConfig == NULL)  {    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;    return HAL_ERROR;  }
  if(heth->gState == HAL_ETH_STATE_READY)  {    /* Config DMA Tx descriptor by Tx Packet info */    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)    {      /* Set the ETH error code */      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;      return HAL_ERROR;    }
    dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
    /* Incr current tx desc index */    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
    /* Start transmission */    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */    //WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));    __DMB();//修改!!    WRITE_REG(heth->Instance->DMACTDTPR, ((uint32_t)(heth->Init.TxDesc + (uint32_t)(ETH_TX_DESC_CNT - 1))));
    tickstart = HAL_GetTick();
    /* Wait for data to be transmitted or timeout occurred */    while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)    {      if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)      {        heth->ErrorCode |= HAL_ETH_ERROR_DMA;        heth->DMAErrorCode = heth->Instance->DMACSR;        /* Set ETH HAL State to Ready */        heth->gState = HAL_ETH_STATE_ERROR;        /* Return function status */        return HAL_ERROR;      }
      /* Check for the Timeout */      if(Timeout != HAL_MAX_DELAY)      {        if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))        {          heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;          heth->gState = HAL_ETH_STATE_ERROR;          return HAL_ERROR;        }      }    }
    /* Return function status */    return HAL_OK;  }  else  {    return HAL_ERROR;  }}
/**  * @brief  Sends an Ethernet Packet in interrupt mode.  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains  *         the configuration information for ETHERNET module  * @param  pTxConfig: Hold the configuration of packet to be transmitted  * @retval HAL status  */HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig){  if(pTxConfig == NULL)  {    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;    return HAL_ERROR;  }
  if(heth->gState == HAL_ETH_STATE_READY)  {    /* Config DMA Tx descriptor by Tx Packet info */    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)    {      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;      return HAL_ERROR;    }
    /* Incr current tx desc index */    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
    __DMB();//修改!!
    /* Start transmission */    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */    //WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));    WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[ETH_TX_DESC_CNT-1]));
    return HAL_OK;
  }  else  {    return HAL_ERROR;  }}

接收的修改

接收相关的函数有2个被修改

uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth){  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;  uint32_t descidx = dmarxdesclist->CurRxDesc;  ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];  uint32_t descscancnt = 0;  uint32_t appdesccnt = 0, firstappdescidx = 0;
  if(dmarxdesclist->AppDescNbr != 0U)  {    /* data already received by not yet processed*/    return 0;  }
  /* Check if descriptor is not owned by DMA */  while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))  {    descscancnt++;
    /* Check if last descriptor */    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)    {      /* Increment the number of descriptors to be passed to the application */      appdesccnt += 1U;
      if(appdesccnt == 1U)      {        WRITE_REG(firstappdescidx, descidx);      }
      /* Increment current rx descriptor index */      INCR_RX_DESC_INDEX(descidx, 1U);
      /* Check for Context descriptor */      /* Get current descriptor address */      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
      if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_OWN)  == (uint32_t)RESET)      {        if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)        {          /* Increment the number of descriptors to be passed to the application */          dmarxdesclist->AppContextDesc = 1;          /* Increment current rx descriptor index */          INCR_RX_DESC_INDEX(descidx, 1U);        }      }      /* Fill information to Rx descriptors list */      dmarxdesclist->CurRxDesc = descidx;      dmarxdesclist->FirstAppDesc = firstappdescidx;      dmarxdesclist->AppDescNbr = appdesccnt;
      /* Return function status */      return 1;    }    /* Check if first descriptor */    else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)    {      WRITE_REG(firstappdescidx, descidx);      /* Increment the number of descriptors to be passed to the application */      appdesccnt = 1U;
      /* Increment current rx descriptor index */      INCR_RX_DESC_INDEX(descidx, 1U);      /* Get current descriptor address */      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];    }    /* It should be an intermediate descriptor */    else    {      /* Increment the number of descriptors to be passed to the application */      appdesccnt += 1U;
      /* Increment current rx descriptor index */      INCR_RX_DESC_INDEX(descidx, 1U);      /* Get current descriptor address */      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];    }  }
  /* Build Descriptors if an incomplete Packet is received */  if(appdesccnt > 0U)  {    dmarxdesclist->CurRxDesc = descidx;    dmarxdesclist->FirstAppDesc = firstappdescidx;    descidx = firstappdescidx;    dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
    for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)    {      WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);      WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
      if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))      {        WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);        SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);      }
      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
      if(dmarxdesclist->ItMode != ((uint32_t)RESET))      {        SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);      }      if(descscancnt < (appdesccnt - 1U))      {        /* Increment rx descriptor index */        INCR_RX_DESC_INDEX(descidx, 1U);        /* Get descriptor address */        dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];      }    }
    /* Set the Tail pointer address to the last rx descriptor hold by the app */    //WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);  }
  /* Fill information to Rx descriptors list: No received Packet */  dmarxdesclist->AppDescNbr = 0U;
  return 0;}
HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth){  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;  uint32_t descindex = dmarxdesclist->FirstAppDesc;  __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];  uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;  uint32_t descscan;
  if(dmarxdesclist->AppDescNbr == 0U)  {    /* No Rx descriptors to build */    return HAL_ERROR;  }
  if(dmarxdesclist->AppContextDesc != 0U)  {    /* A context descriptor is available */    totalappdescnbr += 1U;  }
  for(descscan =0; descscan < totalappdescnbr; descscan++)  {    WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);    WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
    if (READ_REG(dmarxdesc->BackupAddr1) != 0U)    {      WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);    }
    if(dmarxdesclist->ItMode != 0U){      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);    }
    __DMB();//修改!!    SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
    if(descscan < (totalappdescnbr - 1U))    {      /* Increment rx descriptor index */      INCR_RX_DESC_INDEX(descindex, 1U);      /* Get descriptor address */      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];    }  }
  __DMB();//修改!!  /* Set the Tail pointer address to the last rx descriptor hold by the app */  //WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);//修改!!  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));
  /* reset the Application desc number */  WRITE_REG(dmarxdesclist->AppDescNbr, 0);
  /*  reset the application context descriptor */  WRITE_REG(heth->RxDescList.AppContextDesc, 0);
  return HAL_OK;}

其他修改

其实下面的修改无关紧要，因为它会在后面的传输中被修正，但强迫症不能忍啊。

static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth){  ETH_DMADescTypeDef *dmatxdesc;  uint32_t i;
  /* Fill each DMATxDesc descriptor with the right values */  for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)  {    dmatxdesc = heth->Init.TxDesc + i;
    WRITE_REG(dmatxdesc->DESC0, 0x0);    WRITE_REG(dmatxdesc->DESC1, 0x0);    WRITE_REG(dmatxdesc->DESC2, 0x0);    WRITE_REG(dmatxdesc->DESC3, 0x0);
    WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);  }
  heth->TxDescList.CurTxDesc = 0;
  /* Set Transmit Descriptor Ring Length */  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
  /* Set Transmit Descriptor List Address */  WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
  /* Set Transmit Descriptor Tail pointer *///修改!!  WRITE_REG(heth->Instance->DMACTDTPR, ((uint32_t)(heth->Init.TxDesc + (uint32_t)(ETH_TX_DESC_CNT - 1))));//修改!!}
/**  * @brief  Initializes the DMA Rx descriptors in chain mode.  *         called by HAL_ETH_Init() API.  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains  *         the configuration information for ETHERNET module  * @retval None  */static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth){  ETH_DMADescTypeDef *dmarxdesc;  uint32_t i;
  for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)  {    dmarxdesc =  heth->Init.RxDesc + i;
    WRITE_REG(dmarxdesc->DESC0, 0x0);    WRITE_REG(dmarxdesc->DESC1, 0x0);    WRITE_REG(dmarxdesc->DESC2, 0x0);    WRITE_REG(dmarxdesc->DESC3, 0x0);    WRITE_REG(dmarxdesc->BackupAddr0, 0x0);    WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
    /* Set Rx descritors addresses */    WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);  }
  WRITE_REG(heth->RxDescList.CurRxDesc, 0);  WRITE_REG(heth->RxDescList.FirstAppDesc, 0);  WRITE_REG(heth->RxDescList.AppDescNbr, 0);  WRITE_REG(heth->RxDescList.ItMode, 0);  WRITE_REG(heth->RxDescList.AppContextDesc, 0);
  /* Set Receive Descriptor Ring Length */  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
  /* Set Receive Descriptor List Address */  WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
  /* Set Receive Descriptor Tail pointer Address *///修改!!  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));//修改!!}

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