【培训通知】高级数模转换器（ADC）设计课程

通信、汽车、工业、医疗保健、云计算和人工智能等各个领域对更高数据传输速率的需求不断增长，推动了具有更高分辨率的数十万至数百亿模数转换器的持续研发。近年来，交错（TI）模数转换器（ADC）经历了重大发展。SAR 型 ADC 满足了 TI 和大规模 TI 子通道架构的大部分要求。在过去二十年中，SAR ADC 不断超越性能障碍，成为中低分辨率最节能的 ADC 拓扑。值得注意的是，通过采用纯数字或模拟辅助校准技术来解决 TI 实现中信道到信道的非理想性，从而提高了信号到噪声失真（SNDR）性能。为了进一步优化速度、有效位数（ENOB）和功耗，SAR 和流水线拓扑的混合组合得到了越来越多的应用。功能扩展促进了紧凑型 TI SAR ADC 的发展，使其能够实现超过 100GSPS 的采样率，成为大型片上系统 (SoC) 集成的一部分。

本次课程首先深入探讨大规模时间交织 ADC 的交织器拓扑结构，探讨非理想情况、设计注意事项、建模技术和详细案例研究。随后，特别关注对高性能大规模 TI ADC 至关重要的外设块的设计挑战和解决方案，包括输入缓冲器和参考缓冲器。此外，还研究了极限采样器、残差放大器和时钟等关键 SAR ADC 块，通过全面的案例研究介绍了基本概念和先进技术。

The growing demand for higher data rates across various sectors such as communication, automotive, industrial, healthcare, cloud computing, and AI has driven the continuous research and development of multi-tens-of-giga to hundreds-of-giga ADCs with extended resolutions. Time-interleaved (TI) Analog-to-Digital Converters (ADCs) have undergone significant evolution in recent years. SAR-type ADCs have met most of the requirements for TI and Massive TI sub-channel architecture. Over the past two decades, SAR ADCs have consistently surpassed performance barriers, emerging as the most energy-efficient ADC topology for low to medium resolutions. Notably, improvements in Signal-to-Noise-Distortion (SNDR) performance have been achieved through the adoption of pure-digital or analog-assisted calibration techniques to address channel-to-channel non-idealities in TI implementations. Hybrid combinations of SAR and Pipeline topologies are increasingly utilized to optimize speed further, Effective-Number-Of-Bits (ENOBs), and power dissipation. Feature scaling has facilitated the development of compact TI SAR ADCs capable of achieving sampling rates beyond 100GSPS as part of large System-on-Chip (SoC) integration. 

The course begins by delving into interleaver topologies of massive time-interleaved ADCs, exploring non-idealities, design considerations, modeling techniques, and detailed case studies. Subsequently, specific attention is given to the design challenges and solutions of peripheral blocks crucial for high-performance massive TI ADCs, including the input buffer and reference buffer. Additionally, key SAR ADC blocks such as the extreme sampler, residue amplifier, and clocking are examined, covering fundamental concepts and advanced techniques through comprehensive case studies.

本课程的推荐目标受众是希望进入ADC设计领域的模拟和混合信号设计工程师，以及已经在使用 ADC 并有兴趣学习先进的超高速ADC设计技术的人员。希望掌握扎实ADC知识的高年级本科生或研究生。熟悉 ADC的基本概念会有帮助，但不是先决条件。

The recommended target audience for this course is analog and mixed-signal design engineers looking to get into ADC design as well as those already working with ADCs, and interested to learn advanced state-of-the-art ultra-high-speed ADC design techniques. Advanced undergraduate or graduate students who wish to develop a solid knowledge of ADC. Familiarity with fundamental ADC concepts will be beneficial but is not a pre-requisite.

上海林恩信息咨询有限公司

上海集成电路技术与产业促进中心

课程时间：2024年07月16日—17日（2天）

报到注册时间：2024年07月16日，上午8:30-9:00

课程地点：上海集成电路技术与产业促进中心（上海市浦东新区张东路1388号21幢）

课程注册费用：4600元/人；学生价：3600元/人；

4人以上团体报名优惠可协商；

课程注册费用包含授课费、场地租赁费、资料费、课程期间午餐。学员交通、食宿等费用自理。

请各单位收到通知后，积极选派人员参加。报名截止日期为2024年07月12日,请在此日期前将报名回执表发送Email至：

邮件：steven.yu@lynneconsulting.com

报名咨询电话：021-58978665；

或者添加微信：136 7161 3108（手机），暗号：ADC课程。

扫描以下二维码获取报名注册表：

付款：

请于07月12日前将全款汇至以下账户。并备注（ADC课程+单位/学校+姓名）

银行信息：

户  名：上海林恩信息咨询有限公司

开户行：上海银行曹杨支行

帐  号：31658603000624127

支付宝信息：

公司名称：上海林恩信息咨询有限公司

支付宝账号：steven.yu@lynneconsulting.com

2024年07月16日—17日  （两天）

Lecture 1:  Time Interleaver and Massive Time Interleaver (3 hours):

- Application and Technology Motivations

- Time-Interleaved Non-idealities

- Front-End Interleaver Topologies

- Topology Variety Considerations

- Modeling of Interleaver

- Uncertainties and Case Studies

Lecture 2: Wideband Input Buffer and Fast-transient Reference Buffer (2 hours)

- Input Network

- Nonlinearities

- Input Buffer Topologies

- Linearization Techniques

- Reference Ripple

- Reference Buffer Topologies

- Ripple Suppression Techniques

- Case Studies

Lecture #3 – Wideband Samplers (1 hour)

- Sampling Theory

- Sampler Non-idealities

- Bootstrapped Circuits

Lecture #4 – Clocking and Extreme Amplifier Overview (2 hours)

- Effect of Jitter on Sampling

- Low Jitter Clock Receivers

- Power Efficient and Low Jitter CMOS Clock Buffer

- Open-Loop Residue Amplifiers

- Close-Loop Residue Amplifiers

Lecture #5 – State-of-the-Art Low-Resolution High-Speed SAR ADCs (2 hours)

- Single-bit/cycle

- Multi-bit/cycle

- DAC Implementation

- SAR Loop

- SAR Switching Logic

- Redundancy

- Case Studies

Lecture #6 – Extended Resolution and High-Speed: Pipeline-SAR ADCs (2 hours)

- Fundamentals 

- Comparison with SAR ADCs

- Digital Error Correction

- Residue Amplification Errors

- Case Studies

Q&A: Related Problems faced by Participants