FPGA设计中，对SPI进行参数化结构设计

//`define SPI_LINE  //是否是三线SPI`define SPI_FRAME_WIDTH 16 //SPI一帧长度为16`define SPI_INS_WIDTH 8    //SPI指令长`timescale 1ns/1ps////module spi_slave (    input     i_clk               , //work clk    input     i_rst_n             ,        input     i_spi_clk           , //SPI clk    input     i_spi_cs            , //SPI cs
    `ifdef SPI_LINE                 //条件编译    inout     io_spi_sdio              `else    input     i_spi_mosi          , //SPI mosi    output    o_spi_miso            //SPI miso    `endif          );//位宽计算函数function integer clogb2 (input integer depth);begin    for (clogb2=0; depth>0; clogb2=clogb2+1)         depth = depth >>1;                          endendfunctionreg r_cs = 1'b1; //打一拍always @(posedge i_clk)begin    r_cs <= i_spi_cs;endreg [1:0] r_spi_clk_edge = 2'b00; //SPI clk边沿检测always @(posedge i_clk)begin    r_spi_clk_edge <= {r_spi_clk_edge[0],i_spi_clk};end //alwaysreg [clogb2(`SPI_FRAME_WIDTH-1)-1:0] r_spi_cnt = 'd0;always @(posedge i_clk)begin    if (r_cs) //cs为高则归零        r_spi_cnt <= 'd0;    else if (r_spi_clk_edge == 2'b10) //下降沿才计数        r_spi_cnt <= r_spi_cnt + 'd1;end////指令锁存reg [`SPI_INS_WIDTH-1:0] r_ins = 'd0;always @(posedge i_clk)begin    if ((~r_cs) && (r_spi_clk_edge == 2'b01)) //上升沿锁存数据    begin        if ((r_spi_cnt >= 0) && (r_spi_cnt <= `SPI_INS_WIDTH-1))        `ifdef SPI_LINE                 //条件编译            r_ins <= {r_ins[`SPI_INS_WIDTH-2:0],io_spi_sdio};          `else            r_ins <= {r_ins[`SPI_INS_WIDTH-2:0],i_spi_mosi};          `endif     end end////数值写入reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_data_rx = 'd0;always @(posedge i_clk)begin    if ((~r_cs) && (r_spi_clk_edge == 2'b01)) //上升沿锁存数据    begin        if (r_spi_cnt >= `SPI_INS_WIDTH)        `ifdef SPI_LINE            r_data_rx <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio};        `else            r_data_rx <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi};           `endif    endend////用户寄存器定义reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg0 = 'd0;reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg1 = 'd0;reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg2 = 'd0;reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_reg3 = 'd0;////always @(posedge i_clk,negedge i_rst_n)begin    if (~i_rst_n)    begin        r_reg0 <= 'd0;        r_reg1 <= 'd0;        r_reg2 <= 'd0;        r_reg3 <= 'd0;


    end    else if ((~r_ins[`SPI_INS_WIDTH-1]) && (r_spi_cnt == (`SPI_FRAME_WIDTH-1)) && (~r_cs) && (r_spi_clk_edge == 2'b01))    begin    `ifdef SPI_LINE        case (r_ins[`SPI_INS_WIDTH-2:0])            'd0:begin r_reg0 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end            'd1:begin r_reg1 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end            'd2:begin r_reg2 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end            'd3:begin r_reg3 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],io_spi_sdio}; end



        endcase     `else        case (r_ins[`SPI_INS_WIDTH-2:0])            'd0:begin r_reg0 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end            'd1:begin r_reg1 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end            'd2:begin r_reg2 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end            'd3:begin r_reg3 <= {r_data_rx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],i_spi_mosi}; end



        endcase     `endif     end
end////寄存器值读出reg [`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1:0] r_data_tx = 'd0;always @(posedge i_clk)begin    if (r_ins[`SPI_INS_WIDTH-1] && (~r_cs) && (r_spi_clk_edge == 2'b10))    begin         if (r_spi_cnt == (`SPI_INS_WIDTH-1))        begin            case (r_ins[`SPI_INS_WIDTH-2:0])                'd0:begin r_data_tx <= r_reg0; end                 'd1:begin r_data_tx <= r_reg1; end                 'd2:begin r_data_tx <= r_reg2; end                 'd3:begin r_data_tx <= r_reg3; end                 endcase         end        else             r_data_tx <= {r_data_tx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-2:0],1'b0};    end end
////读取输出`ifdef SPI_LINEassign io_spi_sdio = (r_ins[`SPI_INS_WIDTH-1]) ? (((r_spi_cnt>=`SPI_INS_WIDTH) && (r_spi_cnt<`SPI_FRAME_WIDTH)) ? r_data_tx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1] : 1'bz) : 1'bz;`else assign o_spi_miso = ((r_spi_cnt>=`SPI_INS_WIDTH) && (r_spi_cnt<`SPI_FRAME_WIDTH)) ? r_data_tx[`SPI_FRAME_WIDTH-`SPI_INS_WIDTH-1] : 1'b0;`endif
endmodule // end the spi_slave model

//`define SPI_LINE  //是否是三线SPI`timescale 1ns/1psmodule spi_master #(parameter p_spi_frame_width = 16, //SPI单帧长度  parameter p_spi_ins_width = 8   , //指令长度  parameter p_spi_data_width = 8    //读出数据长度 )(    input                                i_clk             , //系统时钟    input                                i_rst_n           ,    input                                i_flag            , //检测到flag的上升沿则启动一次传输,一个时钟周期即可       input     [p_spi_frame_width-1:0]    i_spi_data        ,    output                               o_spi_cs          ,    output                               o_spi_clk         ,
    `ifdef SPI_LINE                 //条件编译    inout                                io_spi_sdio       ,              `else    input                                i_spi_miso        , //SPI miso    output                               o_spi_mosi        , //SPI mosi    `endif         output                               o_transfer_done   , //单次传输完成    output    [p_spi_data_width-1:0]     o_spi_data          //读取数据           );parameter p_clk_fre = 200; //XXM时钟频率parameter p_spi_clk_fre = 0.5*1000; //SPI 时钟速率,表示1Mparameter p_clk_div = p_clk_fre * 1000/p_spi_clk_fre/2-1;parameter p_spi_cnt_max = p_spi_frame_width*2-1;parameter p_spi_ins_max = p_spi_ins_width*2-1;//位宽计算函数function integer clogb2 (input integer depth);begin    for (clogb2=0; depth>0; clogb2=clogb2+1)         depth = depth >>1;                          endendfunction//把最大值赋值给线型，直接用p_clk_div仿真有问题，但实际上板是可以的wire [clogb2(p_clk_div)-1:0] w_clk_div;assign w_clk_div = p_clk_div;////时钟分频reg [clogb2(p_clk_div)-1:0] r_cnt_div = 'd0;always @(posedge i_clk)begin    if (r_cnt_div == w_clk_div)        r_cnt_div <= 'd0;    else         r_cnt_div <= r_cnt_div + 'd1;end //alwayswire w_clk_en; //分频时钟使能assign w_clk_en = (r_cnt_div == w_clk_div) ? 1'b1 : 1'b0;reg [1:0] r_flag_edge = 2'b00;reg [clogb2(p_spi_cnt_max)-1:0] r_spi_cnt = 'd0;always @(posedge i_clk) //flag边沿检测begin    r_flag_edge <= {r_flag_edge[0],i_flag};end//flag信号展宽到低速时钟域reg r_flag_enlarge = 1'b0;always @(posedge i_clk)begin    if (r_flag_edge == 2'b01) //上升沿拉高        r_flag_enlarge <= 1'b1;    else if (r_spi_cnt == p_spi_ins_max) //足够长的高电平才拉低        r_flag_enlarge <= 1'b0;endreg [1:0] r_flag_enlarge_edge = 2'b00;always @(posedge i_clk)begin    if (w_clk_en)        r_flag_enlarge_edge <= {r_flag_enlarge_edge[0],r_flag_enlarge};endreg r_cs = 1'b1;always @(posedge i_clk)begin    if (w_clk_en)    begin        if (r_flag_enlarge_edge == 2'b01) //检测到需要进行SPI操作            r_cs <= 1'b0;        else if (r_spi_cnt == p_spi_cnt_max) //计数到最大值表示一次SPI完成            r_cs <= 1'b1;    endendalways @(posedge i_clk)begin    if (w_clk_en)    begin        if(~r_cs) //在操作区间计数            r_spi_cnt <= r_spi_cnt + 'd1;        else             r_spi_cnt <= 'd0;    end    end////数据传输段reg [p_spi_frame_width-1:0] r_data = 'd0;always @(posedge i_clk)begin    if (w_clk_en)    begin        if (r_flag_enlarge_edge == 2'b01) //上升沿刷入            r_data <= i_spi_data;        else if (r_spi_cnt[0] == 1'b1) //数据移动            r_data <= {r_data[p_spi_frame_width-2:0],1'b1};    endend////数据读取段reg [p_spi_data_width-1:0] r_data_read = 'd0;always @(posedge i_clk)begin    if (w_clk_en)    begin        if (i_spi_data[p_spi_frame_width-1] && (r_spi_cnt > p_spi_ins_max) && (r_spi_cnt[0] == 1'b0)) //是读        `ifdef SPI_LINE            r_data_read <= {r_data_read[p_spi_data_width-2:0],io_spi_sdio};        `else            r_data_read <= {r_data_read[p_spi_data_width-2:0],i_spi_miso};        `endif     end    end////SPI输出段assign o_spi_cs = r_cs;assign o_spi_clk = r_cs ? 1'b0 : r_spi_cnt[0];////SPI SDIO的输入输出切换`ifdef SPI_LINEassign io_spi_sdio = (i_spi_data[p_spi_frame_width-1]) ? (((r_spi_cnt >= 'd0) && (r_spi_cnt <= p_spi_ins_max)) ? r_data[p_spi_frame_width-1] : 1'bz ) : r_data[p_spi_frame_width-1];`else assign o_spi_mosi = r_data[p_spi_frame_width-1];`endif assign o_transfer_done = ((~r_cs) && (r_spi_cnt == p_spi_cnt_max)) ? 1'b1:1'b0;assign o_spi_data = r_data_read;
endmodule // end the spi_master model

`define TRANSFER_NUMBER 8 //操作数为4`define DATA 8'ha5//`define SPI_LINEtimeunit 1ns;timeprecision 1ps;module top;parameter p_sim_end_time = 1000000; //nslogic l_clk = 1'b0;always #2.5 l_clk = ~l_clk;////复位logic l_rst_n  = 1'b0;initial begin    #100 l_rst_n = 1'b1;end

wire io_sdio;wire o_spi_cs;wire o_spi_clk;wire o_transfer_done;wire [7:0] o_spi_data;////多个数据操作模式reg r_flag = 1'b0;reg [1:0] r_first_cnt = 2'b00;always @(posedge l_clk,negedge l_rst_n)begin    if (~l_rst_n)        r_first_cnt <= 2'b00;    else if (r_first_cnt == 2'd3)        r_first_cnt <= r_first_cnt;    else         r_first_cnt <= r_first_cnt + 2'd1;endreg [1:0] r_transfer_done_edge = 2'b00;always @(posedge l_clk)begin    r_transfer_done_edge <= {r_transfer_done_edge[0],o_transfer_done};endreg [3:0] r_transfer_cnt = 4'd0;always @(posedge l_clk)begin    if ((r_first_cnt == 2'd2) && (r_transfer_cnt < `TRANSFER_NUMBER))        r_flag <= 1'b1;    else if ((r_transfer_done_edge == 2'b10) && (r_transfer_cnt < `TRANSFER_NUMBER-1))        r_flag <= 1'b1;    else         r_flag <= 1'b0;        endalways @(posedge l_clk)begin    if (r_transfer_done_edge == 2'b10)        r_transfer_cnt <= r_transfer_cnt + 'd1;endreg [15:0] r_in_data  = 16'd0;always @(*)begin    if (~l_rst_n) //仿真不执行此段仿真会有问题        r_in_data  = 16'h0000;    else     begin     case(r_transfer_cnt)        4'd0:begin  r_in_data  = {8'h00,8'h43}; end         4'd1:begin  r_in_data  = 16'h0132; end         4'd2:begin  r_in_data  = 16'h0245; end         4'd3:begin  r_in_data  = 16'h0367; end         4'd4:begin  r_in_data  = 16'h8000; end         4'd5:begin  r_in_data  = 16'h8100; end         4'd6:begin  r_in_data  = 16'h8200; end         4'd7:begin  r_in_data  = 16'h8300; end 
        default:begin  r_in_data  = 16'h0000; end    endcase    end end
wire w_spi_miso;wire w_spi_mosi;
spi_master inst_spi_master (    .i_clk             (l_clk),    .i_rst_n           (),    .i_flag            (r_flag),    .i_spi_data        (r_in_data),    .o_spi_cs          (o_spi_cs),    .o_spi_clk         (o_spi_clk),    `ifdef SPI_LINE    .io_spi_sdio       (io_sdio),    `else    .i_spi_miso        (w_spi_miso),    .o_spi_mosi        (w_spi_mosi),    `endif    .o_transfer_done   (o_transfer_done),    .o_spi_data        (o_spi_data)    );
spi_slave  inst_spi_slave (    .i_clk                            (l_clk),    .i_rst_n                          (l_rst_n),
    .i_spi_clk                        (o_spi_clk),    .i_spi_cs                         (o_spi_cs),    `ifdef SPI_LINE    .io_spi_sdio                      (io_sdio)    `else    .i_spi_mosi                      (w_spi_mosi),    .o_spi_miso                      (w_spi_miso)    `endif
);
initial begin    #p_sim_end_time $stop;end
    endmodule