基于FPGA的TMDS编码

1    `timescale 1 ps / 1ps2  3    module dvi_encoder (4      input            clkin,    // pixel clock input5      input            rstin,    // async. reset input (active high)6      input      [7:0] din,      // data inputs: expect registered7      input            c0,       // c0 input8      input            c1,       // c1 input9      input            de,       // de input10     output reg [9:0] dout      // data outputs11   );12 13     ////////////////////////////////////////////////////////////14     // Counting number of 1s and 0s for each incoming pixel15     // component. Pipe line the result.16     // Register Data Input so it matches the pipe lined adder17     // output18     ////////////////////////////////////////////////////////////19     reg [3:0] n1d; //number of 1s in din20     reg [7:0] din_q;21 22   //计算像素数据中“1”的个数23     always @ (posedge clkin) begin24     n1d <=#1 din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7];25 26     din_q <=#1 din;27     end28 29     ///////////////////////////////////////////////////////30     // Stage 1: 8 bit -> 9 bit31     // Refer to DVI 1.0 Specification, page 29, Figure 3-532     ///////////////////////////////////////////////////////33     wire decision1;34 35     assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q[0] == 1'b0));36 37     wire [8:0] q_m;38     assign q_m[0] = din_q[0];39     assign q_m[1] = (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]);40     assign q_m[2] = (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]);41     assign q_m[3] = (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]);42     assign q_m[4] = (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]);43     assign q_m[5] = (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]);44     assign q_m[6] = (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]);45     assign q_m[7] = (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]);46     assign q_m[8] = (decision1) ? 1'b0 : 1'b1;47 48     /////////////////////////////////////////////////////////49     // Stage 2: 9 bit -> 10 bit50     // Refer to DVI 1.0 Specification, page 29, Figure 3-551     /////////////////////////////////////////////////////////52     reg [3:0] n1q_m, n0q_m; // number of 1s and 0s for q_m53     always @ (posedge clkin) begin54     n1q_m  <=#1 q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7];55     n0q_m  <=#1 4'h8 - (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]);56     end57 58     parameter CTRLTOKEN0 = 10'b1101010100;59     parameter CTRLTOKEN1 = 10'b0010101011;60     parameter CTRLTOKEN2 = 10'b0101010100;61     parameter CTRLTOKEN3 = 10'b1010101011;62 63     reg [4:0] cnt; //disparity counter, MSB is the sign bit64     wire decision2, decision3;65 66     assign decision2 = (cnt == 5'h0) | (n1q_m == n0q_m);67     /////////////////////////////////////////////////////////////////////////68     // [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)]69     /////////////////////////////////////////////////////////////////////////70     assign decision3 = (~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m));71 72     ////////////////////////////////////73     // pipe line alignment74     ////////////////////////////////////75     reg       de_q, de_reg;76     reg       c0_q, c1_q;77     reg       c0_reg, c1_reg;78     reg [8:0] q_m_reg;79 80     always @ (posedge clkin) begin81     de_q    <=#1 de;82     de_reg  <=#1 de_q;83     84     c0_q    <=#1 c0;85     c0_reg  <=#1 c0_q;86     c1_q    <=#1 c1;87     c1_reg  <=#1 c1_q;88 89     q_m_reg <=#1 q_m;90     end91 92     ///////////////////////////////93     // 10-bit out94     // disparity counter95     ///////////////////////////////96     always @ (posedge clkin or posedge rstin) begin97     if(rstin) begin98       dout <= 10'h0;99       cnt <= 5'h0;100    end else begin101      if (de_reg) begin102      if(decision2) begin103        dout[9]   <=#1 ~q_m_reg[8]; 104        dout[8]   <=#1 q_m_reg[8]; 105        dout[7:0] <=#1 (q_m_reg[8]) ? q_m_reg[7:0] : ~q_m_reg[7:0];106107        cnt <=#1 (~q_m_reg[8]) ? (cnt + n0q_m - n1q_m) : (cnt + n1q_m - n0q_m);108      end else begin109        if(decision3) begin110        dout[9]   <=#1 1'b1;111        dout[8]   <=#1 q_m_reg[8];112        dout[7:0] <=#1 ~q_m_reg[7:0];113114        cnt <=#1 cnt + {q_m_reg[8], 1'b0} + (n0q_m - n1q_m);115        end else begin116        dout[9]   <=#1 1'b0;117        dout[8]   <=#1 q_m_reg[8];118        dout[7:0] <=#1 q_m_reg[7:0];119120        cnt <=#1 cnt - {~q_m_reg[8], 1'b0} + (n1q_m - n0q_m);121        end122      end123      end else begin124      case ({c1_reg, c0_reg})125        2'b00:   dout <=#1 CTRLTOKEN0;126        2'b01:   dout <=#1 CTRLTOKEN1;127        2'b10:   dout <=#1 CTRLTOKEN2;128        default: dout <=#1 CTRLTOKEN3;129      endcase130131      cnt <=#1 5'h0;132      end133    end134    end135    136  endmodule