用生成式AI设计芯片，实例1：从有限状态机图片直接生成SV代码

// Vending machine FSM// Disclaimer: This code is not tested for correctness
module vending_machine (  input clk,  input reset,  input coin_inserted,  input product_selected,  input product_dispensed,
  output reg dispense_product,  output reg return_coin);
  // Define the states  localparam [2:0] IDLE = 3'b000;  localparam [2:0] COIN_INSERTED = 3'b001;  localparam [2:0] PRODUCT_SELECTED = 3'b010;  localparam [2:0] PRODUCT_DISPENSED = 3'b011;  localparam [2:0] OUT_OF_STOCK = 3'b100;
  // Define the registers  reg [2:0] current_state;
  // Transition logic  always @(posedge clk or posedge reset) begin    if (reset) begin      current_state <= IDLE;    end else begin      case (current_state)        IDLE: begin          if (coin_inserted) begin            current_state <= COIN_INSERTED;          end else begin            current_state <= IDLE;          end        end        COIN_INSERTED: begin          if (product_selected) begin            current_state <= PRODUCT_SELECTED;          end else begin            current_state <= COIN_INSERTED;          end        end        PRODUCT_SELECTED: begin          if (product_dispensed) begin            current_state <= PRODUCT_DISPENSED;          end else if (out_of_stock) begin            current_state <= OUT_OF_STOCK;          end else begin            current_state <= PRODUCT_SELECTED;          end        end        PRODUCT_DISPENSED: begin          current_state <= IDLE;        end        OUT_OF_STOCK: begin          current_state <= IDLE;        end      endcase    end  end
  // Output logic  always @(posedge clk) begin    case (current_state)      PRODUCT_DISPENSED: begin        dispense_product <= 1'b1;      end      default: begin        dispense_product <= 1'b0;      end    endcase  end
  always @(posedge clk) begin    case (current_state)      OUT_OF_STOCK: begin        return_coin <= 1'b1;      end      default: begin        return_coin <= 1'b0;      end    endcase  end
endmodule