如果FPGA没有外部时钟源输入，可以通过调用STARTUP原语，来使用FPGA芯片内部的时钟和复位信号，Spartan-6系列内部时钟源是50MHz，Artix-7、Kintex-7等7系列FPGA是65MHz。
wire clk_50m;
wire rst_n;
STARTUP_SPARTAN6 STARTUP_SPARTAN6_inst (
.CFGMCLK(clk_50m), // 1-bit output: Configuration internal oscillator clock output.
.EOS(rst_n), // 1-bit output: Active high output signal indicates the End Of Configuration.
);
wire clk_65m;
wire rst_n;
STARTUPE2 STARTUPE2_ut0(
.CFGMCLK(clk_65m), // 1-bit output: Configuration internal oscillator clock output 65MHz.
.EOS(rst_n) // 1-bit output: Active high output signal indicating the End Of Startup.
);
分别可以参考文档：
UG380:Spartan-6 FPGA Configuration
UG470:7 Series FPGAs Configuration
