FPGA笔记之按键消抖

//计数延迟5ms    always@(posedge clk or negedge rst_n)    begin        if(rst_n == 1'b0)               delay_cnt <= 20'd0;        else if(cnt_start == 1'b1)            delay_cnt <= delay_cnt + 20'd1;        else            delay_cnt <= 20'd0;    end        always@(posedge clk or negedge rst_n)    begin        if(rst_n == 1'b0)               cnt_finish <= 1'b0;        else if(delay_cnt == 20'd499999)            cnt_finish <= 1'b1;        else            cnt_finish <= 1'b0;    end

//FSM for the key    always@(posedge clk or negedge rst_n)    begin        if(rst_n == 1'b0)        begin            state <= IDLE;            cnt_start <= 1'b0;            key_o_r <= 1'b1;        end        else             case(state)                IDLE    :begin                    if(key_neg == 1'b1)                    begin                        cnt_start <= 1'b1;                        state <= FILTER0;                    end                    else                        state <= IDLE;                end                FILTER0 :begin                    if(cnt_finish == 1'b1)                    begin                        cnt_start <= 1'b0;                        key_o_r <= 1'b0;                                            state <= DOWN;                    end                    else if(key_pos == 1'b1)                    begin                        state <= IDLE;                        cnt_start <= 1'b0;                                          end                    else                     begin                        state <=  FILTER0;                    end                     end                DOWN    :begin                    if(key_pos == 1'b1)                    begin                        state <= FILTER1;                        cnt_start <= 1'b1;                    end                    else                     begin                        state <= DOWN;                    end                end                FILTER1 :begin                    if(cnt_finish == 1'b1)                    begin                        cnt_start <= 1'b0;                        state <= IDLE;                        key_o_r <= 1'b1;                    end                    else if(key_neg == 1'b1)                    begin                        state <= DOWN;                        cnt_start <= 1'b0;                    end                    else                     begin                        state <=  FILTER1;                    end                         end                default :begin                    state <= IDLE;                    key_o_r <= 1'b1;                    cnt_start <= 1'b0;                end            endcase    end