如何用FPGA通过模拟的光敏电阻测光？

module ADC_top (  clk_in,  rstn,  digital_out,  analog_cmp,    analog_out,  sample_rdy);
parameter ADC_WIDTH = 8,              // ADC Convertor Bit PrecisionACCUM_BITS = 10,            // 2^ACCUM_BITS is decimation rate of accumulatorLPF_DEPTH_BITS = 3,         // 2^LPF_DEPTH_BITS is decimation rate of averagerINPUT_TOPOLOGY = 1;         // 0: DIRECT: Analog input directly connected to + input of comparitor                            // 1: NETWORK:Analog input connected through R divider to - input of comp.
//input portsinput  clk_in;        // 62.5Mhz on Control Demo boardinput  rstn;   input  analog_cmp;      // from LVDS buffer or external comparitor
//output portsoutput  analog_out;         // feedback to RC networkoutput  sample_rdy;output [7:0] digital_out;   // connected to LED field on control demo bd. 
//**********************************************************************////  Internal Wire & Reg Signals////**********************************************************************wire              clk;wire              analog_out_i;wire              sample_rdy_i;wire [ADC_WIDTH-1:0]      digital_out_i;wire [ADC_WIDTH-1:0]      digital_out_abs;


assign clk = clk_in;

//***********************************************************************////  SSD ADC using onboard LVDS buffer or external comparitor////***********************************************************************sigmadelta_adc #(  .ADC_WIDTH(ADC_WIDTH),  .ACCUM_BITS(ACCUM_BITS),  .LPF_DEPTH_BITS(LPF_DEPTH_BITS)  )SSD_ADC(  .clk(clk),  .rstn(rstn),  .analog_cmp(analog_cmp),  .digital_out(digital_out_i),  .analog_out(analog_out_i),  .sample_rdy(sample_rdy_i)  );
assign digital_out_abs = INPUT_TOPOLOGY ? ~digital_out_i : digital_out_i;  
//***********************************************************************////  output assignments////***********************************************************************

assign digital_out   = ~digital_out_abs;   // invert bits for LED display assign analog_out    =  analog_out_i;assign sample_rdy    =  sample_rdy_i;
endmodule

module sigmadelta_adc (  clk,                      rstn,                     digital_out,              analog_cmp,                analog_out,               sample_rdy);            
parameter ADC_WIDTH = 8,              // ADC Convertor Bit PrecisionACCUM_BITS = 10,            // 2^ACCUM_BITS is decimation rate of accumulatorLPF_DEPTH_BITS = 3;         // 2^LPF_DEPTH_BITS is decimation rate of averager
//input portsinput  clk;                            // sample rate clockinput  rstn;                           // async reset, asserted lowinput  analog_cmp ;                    // input from LVDS buffer (comparitor)
//output portsoutput  analog_out;                     // feedback to comparitor input RC circuitoutput  sample_rdy;                     // digital_out is readyoutput [ADC_WIDTH-1:0]  digital_out;    // digital output word of ADC

//**********************************************************************////  Internal Wire & Reg Signals////**********************************************************************reg                         delta;          // captured comparitor outputreg [ACCUM_BITS-1:0]      sigma;          // running accumulator valuereg [ADC_WIDTH-1:0]          accum;          // latched accumulator valuereg [ACCUM_BITS-1:0]      counter;        // decimation counter for accumulatorreg              rollover;       // decimation counter terminal countreg              accum_rdy;      // latched accumulator value 'ready' 



//***********************************************************************////  SSD 'Analog' Input - PWM////  External Comparator Generates High/Low Value////***********************************************************************
always @ (posedge clk)begin    delta <= analog_cmp;        // capture comparitor outputend
assign analog_out = delta;      // feedback to comparitor LPF
//***********************************************************************////  Accumulator Stage////  Adds PWM positive pulses over accumulator period////***********************************************************************
always @ (posedge clk or negedge rstn)begin  if( ~rstn )     begin    sigma       <= 0;    accum       <= 0;    accum_rdy   <= 0;    end else begin        if (rollover) begin            // latch top ADC_WIDTH bits of sigma accumulator (drop LSBs)            accum <= sigma[ACCUM_BITS-1:ACCUM_BITS-ADC_WIDTH];            sigma <= delta;         // reset accumulator, prime with current delta value        end else begin            if (&sigma != 1'b1)         // if not saturated                sigma <= sigma + delta; // accumulate         end        accum_rdy <= rollover;     // latch 'rdy' (to align with accum)    endend


//***********************************************************************////  Box filter Average////  Acts as simple decimating Low-Pass Filter////***********************************************************************
box_ave #(    .ADC_WIDTH(ADC_WIDTH),    .LPF_DEPTH_BITS(LPF_DEPTH_BITS))box_ave (    .clk(clk),    .rstn(rstn),    .sample(accum_rdy),    .raw_data_in(accum),    .ave_data_out(digital_out),    .data_out_valid(sample_rdy));
//************************************************************************//// Sample Control - Accumulator Timing//  //************************************************************************
always @(posedge clk or negedge rstn)begin  if( ~rstn ) begin    counter <= 0;    rollover <= 0;    end  else begin    counter <= counter + 1;       // running count    rollover <= &counter;         // assert 'rollover' when counter is all 1's    endend

module box_ave (  clk,  rstn,  sample,  raw_data_in,  ave_data_out,    data_out_valid);
parameter ADC_WIDTH = 8,        // ADC Convertor Bit PrecisionLPF_DEPTH_BITS = 4;         // 2^LPF_DEPTH_BITS is decimation rate of averager
//input portsinput  clk;                                // sample rate clockinput  rstn;                              // async reset, asserted lowinput  sample;                        // raw_data_in is good on rising edge, input  [ADC_WIDTH-1:0]  raw_data_in;    // raw_data input
//output portsoutput [ADC_WIDTH-1:0]  ave_data_out;    // ave data outputoutput data_out_valid;                      // ave_data_out is valid, single pulse
reg [ADC_WIDTH-1:0]  ave_data_out;    //**********************************************************************////  Internal Wire & Reg Signals////**********************************************************************reg [ADC_WIDTH+LPF_DEPTH_BITS-1:0]      accum;          // accumulatorreg [LPF_DEPTH_BITS-1:0]                count;          // decimation countreg [ADC_WIDTH-1:0]            raw_data_d1;    // pipeline register
reg sample_d1, sample_d2;                               // pipeline registersreg result_valid;                                       // accumulator result 'valid'wire accumulate;                                        // sample rising edge detectedwire latch_result;                                      // latch accumulator result
//***********************************************************************////  Rising Edge Detection and data alignment pipelines////***********************************************************************always @(posedge clk or negedge rstn)begin  if( ~rstn ) begin    sample_d1 <= 0;      sample_d2 <= 0;        raw_data_d1 <= 0;    result_valid <= 0;  end else begin    sample_d1 <= sample;                // capture 'sample' input    sample_d2 <= sample_d1;             // delay for edge detection    raw_data_d1 <= raw_data_in;       // pipeline     result_valid <= latch_result;    // pipeline for alignment with result  endend
assign    accumulate = sample_d1 && !sample_d2;      // 'sample' rising_edge detectassign    latch_result = accumulate && (count == 0);  // latch accum. per decimation count
//***********************************************************************////  Accumulator Depth counter////***********************************************************************always @(posedge clk or negedge rstn)begin  if( ~rstn ) begin    count <= 0;      end else begin      if (accumulate)  count <= count + 1;         // incr. count per each sample  endend

//***********************************************************************////  Accumulator////***********************************************************************always @(posedge clk or negedge rstn)begin  if( ~rstn ) begin    accum <= 0;    end else begin        if (accumulate)            if(count == 0)                      // reset accumulator            accum <= raw_data_d1;           // prime with first value            else                accum <= accum + raw_data_d1;   // accumulate  end  end  //***********************************************************************////  Latch Result////  ave = (summation of 'n' samples)/'n'  is right shift when 'n' is power of two////***********************************************************************always @(posedge clk or negedge rstn)begin  if( ~rstn ) begin        ave_data_out <= 0;    end else if (latch_result) begin            // at end of decimation period...        ave_data_out <= accum >> LPF_DEPTH_BITS;    // ... save accumulator/n result    endend
assign data_out_valid = result_valid;       // output assignment
endmodule