“巧妇难为无米之炊”，半导体设备落后延宕14nm工艺

台积电研发高管在Semicon台湾国际半导体展的一次演讲中表示，留给台积电决定如何在2015年投产14nm芯片的时间越来越短，而资本设备厂商却没能跟上进度。

台积电认为公司需要转向下一代光刻技术和450mm晶圆才能让14nm芯片成本变得经济，但资本设备厂商在这两块的进度可能都跟不上。“我们每天都越来越担心”台积电研发高级副总裁蒋尚义(Shang-Yi Chiang)说道。

晶圆厂需要每小时输出100片以上的晶圆。但到目前EUV(Extreme Ultraviolet)光刻每小时最多只能生产五片晶圆。而两种采用多电子光束直写(multiple e-beam direct write)的方法每小时还不到一片。

类似的，台积电“几个月前就希望生产450mm晶圆，但一些资本设备厂商认为这样太激进，现在我们不知道具体日程会是什么样子”。演讲结束后蒋尚义对电子工程专辑说，“我们得像130nm那代产品一样，当时有些用200mm晶圆生产、有些用300mm晶圆。”

台积电目前计划在新竹的Fab 12晶圆厂建立一条450mm晶圆试产线，随后在台中建立一条量产生产线。更大的晶圆不但需要跟上摩尔定律，也需要将晶圆成本降低最多30%。

450mm晶圆可以减少晶圆厂所用晶圆数量，大幅降低土地和人员成本。通过450mm晶圆满足等同于3200万片8英寸晶圆的需求，台积电需要聘请20000名工程师运作22家晶圆厂。蒋尚义估计如果使用今天的300mm晶圆完成相同的产量就需要29座晶圆厂和27000名工程师。

他说：“450mm晶圆不存在技术问题，但面临着经济问题，而后者在今天比前者更加重要。”

光刻方面，现在的193nm浸润式(immersion)系统可以同时满足台积电目前的28nm节点和未来的20nm节点。但到了20nm，晶圆厂需要进行双重曝光(double patterning)，让晶圆在某些曝光流程上走两次以画出更好的线。

到14nm以后，浸润式系统所需要的双重曝光次数会让成本对于很多客户来说变得过高。因此台积电两周前就开始测试ASML的一台3100系列EUV原型机。此外台积电还在测试来自Mapper Lithography BV的电子光束系统，明年还会安装一台KLA Tencor的设备。

蒋尚义警告说：“如果我们没法让EUV或电子光束设备达到100晶圆每小时的输出量，出于成本因素的考虑，将只有很少的客户会愿意采用更高级的节点。”

台积电希望在2015年投产14nm制程，因此“我们必须在明年早些时候做出(关于光刻的)决定，”蒋尚义说道，“如果我们决定采用193nm浸润，未来很难切换到EUV，设计原则也取决于光刻技术的选择，时间越来越少。”

台积电：450mm晶圆能够降低工程人员与土地投入

下一页：新晶体管需要14nm

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新晶体管需要14nm

蒋尚义表示浸润光刻到14nm将会过于昂贵，超过半数资本设备节点成本指南。尽管EUV和电子光束设备耗资巨大，可能会高达1.2亿美元，但它们还是比双重曝光下采用浸润系统更便宜。

蒋尚义说电子光束和EUV系统开支基本相当。但目前测试中的电子光束系统不需要掩膜，因此使用成本将比EUV略低。

台积电：浸润的光刻成本在14nm将会飞涨

布鲁塞尔IMEC研究咨询公司首席执行官Luc Van den hove表示EUV拥有“最为广阔的支持，是最有可能胜出的选择”。他在另一个场合下提到“但今明两年我们得测试这种技术的生产是否值得。”

IMEC已经运行一台预生产型ASML 3100系统生产晶圆达三个月，Van den hove说：“这期间输出速度有所改善，但进度还是太慢，未来必须加速。”

EUV光源的功率还是太低，尽管已经有两种途径创造光源。“进度不够理想，这是目前优先级最高的问题”，曾经负责过IMEC光刻项目的Van den hove说道。

就好像资本设备问题还不够似的，台积电预计需要在14nm改用新的晶体管设计，比如FinFET。英特尔宣布从20nm开始采用这种3D晶体管设计。

台积电和GlobalFoundries相信平面晶体管可以一直用到20nm。但两家公司也都预期会在14nm转向FinFET这样的3D晶体管或FDSOI。

Van den hove评论说FinFET“最有可能被选中。此外我们相信必须再来一次技术突破才能使用超高移动性材料，例如锗p-channel或10nm节点n-channel所用的三五族(III-IV)材料。”

蒋尚义说好消息是出人意料的创新在过去几代成功推动业界翻越障碍，打破十次摩尔定律将终结的预测。他根据可行性演示预测目前已定义的技术将能把CMOS带向7nm。

点击参考原文：TSMC says equipment vendors late for 14 nm

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TSMC says equipment vendors late for 14 nm

Rick Merritt

Time is running out to make critical decisions for how to make 14-nm chips expected to hit production in 2015, and capital equipment vendors are falling behind. That was the upshot of a talk by the top R&D executive at TSMC at Semicon Taiwan here.

TSMC believes it needs to move to next-generation lithography and 450-mm wafers to make 14-nm chips cost effectively, but capital equipment makers threaten to miss the foundry's schedule on both fronts. "Every day we become more and more concerned," said Shang-Yi Chiang, senior vice president of R&D of TSMC.

Fabs need throughput of more than 100 wafers per hour. But so far extreme ultraviolet (EUV) lithography offers just five wafers per hour at best. Two alternatives using multiple e-beam direct write approaches get less than one.

Similarly, TSMC "put out our wish list for 450-mm wafers a few months ago, but some in the capital equipment industry felt it was too aggressive so now we don’t know" what the schedule will be, Chiang said to EE Times after his talk. "We may have to do what we did at the 130-nm generation when some capacity was on 200- and some on 300-mm wafers," he said.

TSMC currently plans to bring up a pilot 450-mm wafer line at its Fab 12 in Hsinchu, followed by a production line in Taichung. The larger wafers are needed both to help keep pace with Moore's Law and to lower wafer costs as much as 30 percent.

The 450-nm wafers enable foundries to use fewer fabs, saving significant money on both land and labor costs. To meet expected demand for 32 million eight-inch equivalent wafers, TSMC could hire 20,000 engineers to run 22 plants. If it has to use today's 300-mm wafers the same output would require 29 plants and 27,000 engineers, Chiang estimated.

"450-mm wafers are not a technical issue but an economic issue which is probably more important than technical issue these days," Chiang said.

In lithography, today's 193-nm immersion systems will serve both the 28-nm node TSMC is ramping now and the next-generation 20-nm node. But at 20 nm, fabs will need to use double patterning, essentially running wafers through some exposure processes twice to draw finer lines.

At 14 nm the amount of double patterning with immersion systems could become prohibitively expensive for many customers. So TSMC will start testing a prototype 3100 series EUV machine from ASML in two weeks. It has already been testing an e-beam system from Mapper Lithography BV and will install another from KLA Tencor next year.

"If we cannot get EUV or e-beam to 100 wafers per hour throughput, we see few customers will be willing to continue migrating to finer technology nodes because of the cost," he warned.

TSMC hopes to ramp a 14-nm process in 2015 so "we have to make this decision [on lithography] early next year," Chiang said. "If we focus on using 193-nm immersion it becomes difficult to switch to EUV later on, [and] design rules will be defined based on the choice of lithography, so time is running out," he said.

450mm wafers cut engineering and land costs, TSMC said.

New transistors needed at 14nm

Lithography costs soar for immersion at 14nm, TSMC said.

Chiang suggested immersion lithography would be too expensive at 14 nm, exceeding traditional guidelines of half the capital equipment costs for a node. Despite the enormous costs of EUV and e-beam machines, estimated at as much as $120 million, they are still cheaper than immersion given the double patterning problems.

E-beam and EUV systems cost roughly the same. But E-beam systems currently under test do not require masks so could slightly cheaper to use than EUV, Chiang said.

EUV has "the broadest support and is the most likely route" forward, said Luc Van den hove, chief executive of the Imec research consortium based outside Brussels. "But this year and next we have to demo the production worthiness of this technology," Van den hove said in a separate talk.

Imec has been running wafers through an ASML 3100 pre-production system for three months "and we've seen improvement in throughput, but progress has been too slow and we have to further accelerate it," he said.

The power of the EUV source light is still too low, despite defining two approaches to creating the light source. "Progress has not been sufficient, and this is one of the highest priorities," said Van den hove who once ran Imec's lithography program.

As if the capital equipment problems were not enough, TSMC expects it will need to transition to a new transistor design at 14 nm, likely a FinFET. Intel announced plans to use such a 3-D transistor design starting at 20 nm.

Both TSMC and GlobalFoundries believe planar transistors can be used down to 20 nm. But they both expect to make the switch to 3-D structures such as FinFETs or fully depleted SOI at 14 nm.

Van den hove said FinFETs "are probably the most likely way. Beyond that we believe another technology breakthrough will be needed likely using super-high mobility materials such as germanium p-channel and III-IV materials for n-channels for 10 nm nodes," he added.

The good news is unexpected innovations have powered the industry past roadblocks in previous generations, despite as many as ten past predictions that Moore's law would end, said Chiang of TSMC. Based on feasibility demonstrations, he projected currently defined technologies could take CMOS scaling to geometries as fine as 7 nm.