PCIe 4.0速率可望翻番，铜线技术仍能发挥余热

产业标准组织PCI Special Interest Group (SIG)已经确定，他们将在光学连结时代来临之前，为铜线连结订出至少再一版新的高速PCI Express ( PCIe ) 规格。采用此第四代PCIe标准的产品预计在4年内问世，届时预期可支持16 GTransfers/second (GT/s)的传输速率。

“我们所得到的最初报告显示，PCIe 4.0是可行的──我们还需要厘清细节，但那是可行的；”PCI SIG主席Al Yanes在该组织近日于美国举行的年度开发者大会(developers conference)期间的记者会上表示。目前正有一个成员包括AMD、HP、IBM与Intel等厂商在内的探勘小组，用芯片、通道、封包、插槽等对新版标准规格进行模拟，他们确认16 GT/s的速率是可行的，而最终报告将在今年底公布。

PCI SIG串列式通讯技术组主席Ramin Neshanti表示：“我们认为铜线技术还能有更进一步的发挥，因此还没有转向光学技术。”PCI SIG花费近4年时间才敲定8 GT/s的第三代PCIe规格，因为该新版规格需要全新的讯号编码与等化(encoding and equalization)架构；第四代PCIe所需时间应该差不多，但Neshanti表示，这一次工作重点会比较少着墨硅芯片部分，而主要是在于讯号通过的板级通道(board-level channel)部分。

值得一提的是，PCIe 4.0的传输距离将会由3.0版的20英吋，缩短到约8~12英吋；如果工程师需要更长的传输距离，会需要用到中继器(repeater)，这会成为PCIe芯片颇具潜力的应用领域。此外，4.0版的电路板可能需要采用新的材料、通孔(via)设计，与改善讯号完整性的向下相容连接器设计，以减少阻抗不连续(impedance discontinuities)；“我们认为我们在芯片微缩方面已经达到极限了；”Neshanti同时也在Intel担任I/O标准部门的经理。

这对于过去从未要求电路板制造商做出大幅改变的PCIe社群来说是个重大转变，通常PCI SIG都把最困难的问题丢给芯片厂商，例如AMD、Intel、NEC等等，为供应链中技术反而比较不复杂的PC主板与系统制造商减轻许多负担。

然而，芯片领域还是得面临许多转变。PCIe 3.0版的收发器(transceiver)是首度采用讯息讯号(massage signal)技术，以及单输出决策回授等化器(decision feedback equalization，DFE)；第四代的收发器会需要用到多输出DFE，但还不清楚会需要用到多少输出。

“新版标准也会带来测试设备业者的大量投资需求，他们可能会开发一些非常创新的探测解决方案(probing solutions)，无论是芯片上的或是以某种外挂的方式。”Neshanti表示，包括Agilent、LeCroy与Tektroinix都是有参与新版标准订定的量测业者：“但我们还不知道哪种技术会领先加快脚步。”

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PCIe 3.0产品已经进入相容性测试与除错阶段

据了解，目前PCIe 4.0标准工作主要聚焦于物理层设计的电气与模拟层面；随着时间推移，探勘工作将会转向逻辑层，以及减少延迟(latency reduction)、前向纠错(forward error correction) 、更深层管线(deeper pipelining)与错误报告/控制等领域的协议改善。

总而言之，新一代标准也会导致成本的增加，特别是需要维持目前较长传输距离的那些应用；但PCI SIG会致力于将额外成本缩到最小：“PCIe能够生生不息，就是因为其无所不在( ubiquity)与低廉成本。”Neshanti表示。

市场对于速度的需求是显著的，特别是绘图卡与网路交换器等耗频宽的应用，都是推动PCIe 4.0 的力量；双埠40Gbps乙太网路与單埠100G乙太网路板卡的设计厂商，也会需要该4.0标准，以避免可能得用到16路(lane) PCIe 3.0 时所增加的成本。“转接器厂商会因为成本因素，偏好采用8路的配置。”Yane解释。

在此同时，工程师们正在将8GT/s的PCIe 3.0产品推向市场；至少有14家包括IP供应商、软体厂商与量测业者，已宣布支援PCIe 3.0。到目前为止，已有来自一线PC供应商的23款转接卡、19款系统，参与了PCIe 3.0的相容性测试大会(plugfest)：“他们提供的产品都在原型阶段，还没完成相容性的除错，因此也还没准备好上市。”Yanes表示。

PCI SIG 预期在明年初公布通过相容性测试的产品清单，并将在今年于美国硅谷与台湾再举办三场测试大会。“PCIe 3.0在电子设计方面比前几代标准复杂得多，因此我们也正在收集来自成员开发第一代产品的经验回馈。”Neshanti 表示。

点击参考原文：PCI Express poised for 2x upgrade

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PCI Express poised for 2x upgrade

Rick Merritt

The PCI Special Interest Group has determined it can squeeze out of copper links at least one more high speed version of PCI Express before a likely transition to optical interconnects. PCIe Gen 4 is expected to deliver at least 16 GTransfers/second when it debuts in products in about four years.

"The initial report we got yesterday is a PCI Express 4.0 is feasible--we have to work out the details, but it is feasible," said Al Yanes, president of the PCI SIG, speaking in a press briefing at the group's annual developers conference.

A exploratory group including members from AMD, Hewlett-Packard, IBM and Intel are conducting simulations using chip, channel, packet and socket data. They have determined throughput of at least 16 GT/s is possible and are expected to deliver a final report before the end of the year.

"We think we can eke out one more turn of the crank out of copper, so we are not looking at optics yet," said Ramin Neshanti, chairman of the PCI SIG's serial communications working chair.

It took the PCI SIG about four years to hammer out its 8 GT/s PCIe Gen 3 spec which required new signal encoding and equalization schemes. The Gen 4 spec should take a similar period, but this time the focus will be less on silicon and more on the board-level channels through which signals pass, Neshanti said.

Specifically, Gen 4 will probably be limited to distances of about eight to 12 inches compared to 20 inches for Gen 3. Engineers wanting longer reaches will need to use repeaters, a potential growth area for PCIe silicon.

The Gen 4 boards may need to use new materials, via designs and backwards-compatible connectors designed for improved signal integrity to reduce impedance discontinuities. "We think we have achieved about as much as we can scaling silicon," said Neshanti who also serves as an I/O standards manager at Intel.

That's a big shift for the PCIe community which has not previously required major changes of board makers. Typically the PCI SIG has thrown its hardest problems to chip makers such as AMD, Intel, NEC and others to ease problems for its less technically sophisticated supply chain among high volume PC board and system makers.

Nevertheless, some significant silicon shifts are ahead. Transceivers for Gen 3 were the first to use techniques to massage signals, adopting single-tap decision feedback equalization (DFE).

Gen 4 transceivers will need to use multi-tap DFE. How many taps they will need is not yet clear.

"There also will be heavy investments needed from test equipment vendors to do some very creative probing solutions either on chip or somehow as an add-in," said Neshanti. Agilent, LeCroy and Tektronix are among the testers involved in the work, "but we don’t know which will step up first," he said.

Killing bugs in PCIe Gen 3 products

Work has so far focused on electric and analog aspects of the physical-layer design for PCIe Gen 4. Over time, exploration will start on logical-layer and protocol improvements in areas such as latency reduction, forward error correction, deeper pipelining and error reporting and control.

At the end of the day, costs are expected to increase with the new generation, especially for applications that need to maintain today's longer distances. But the group aims to keep additional costs to a minimum.

"PCI Express lives and breathes because of its ubiquity and that comes based on its low cost," said Neshanti.

The need for speed is clear. Graphics and network switches are among the most bandwidth-hungry applications driving Gen 4. Designers of dual-port 40 Gbit/s Ethernet and single-port 100G Ethernet boards want Gen 4 to avoid the costs of supporting the pins they otherwise need for 16 lanes of PCIe Gen 3.

"Adapter vendors like to be around [eight-lane] implementations for cost reasons," said Yanes.

Meanwhile, engineers are making progress getting 8 GT/s PCIe 3.0 products out the door. At least 14 companies with building block cores, software or testers have announced Gen 3 support.

To date about 23 adapter cards and 19 systems from top PC makers have participated in the PCI SIG's Gen 3 plugfests. "Their products are in prototype phase and haven’t achieved full debug interoperability, so they are not ready to announce them," said Yanes.

The PCI SIG hopes to publish by early next year a list of products that have passed interop tests. The group plans at least three more plugfests in Silicon Valley and Taiwan this year.

"PCI Express Gen 3 is more sophisticated in its electrical design [than past PCI SIG standards], so we are giving members more feedback on how they are doing" with their first products, said Neshanti.

Anticipating the future, PLX Technology demoed at the PCI dev con eight lanes of PCI Express 3.0 linking systems over optical cables at 64 Gbits/s.