USB 3.0有望成为芯片互连标准

两个产业组织正计划整合他们的技术，目的是为下一代行动硅芯片定义出一种新的高速、低功耗芯片-芯片接口。两个组织分别是USB 3.0推动小组，以及MIPI联盟，他们希望在明年初完成初步的共同规范。

这个'超高速芯片间规范'(Superspeed Inter-Chip,SSIC)最初预计支援1.2~2.9Gb/s的实体层数据传输率，最终还希望延伸到5.8Gb/s。此外，它还为10Kb/s及600Mb/s之间的数据率规划了一个低功耗模式。

SSIC的目标功耗大约是每b/s时1~5皮焦耳(picojoules)，这主要取决于使用模式。在高速模式下，平均总功耗大约为20mW。

这项努力基本上结合了M-PHY规格，这是MIPI联盟定义的低功耗实体层技术，另外还包括媒体存取控制器以及更高层的USB3.0规范软件。USB 3.0推动小组旗下的工作小组成员包含了英特尔、ST Ericsson和德州仪器并大约在一个月开始商议该规范。

该工作小组目前正在决定要使用USB 3.0规范中的哪些部份做为选项，因为他们可能并不需要芯片接口。“我们希望用现有IP来降低设计成本和上市时间──这与软件再使用有关，”MIPI副主席暨TI OMAP产品经理Brian Carlson说。

SSIC的目标是成为芯片间连接(ICC)的后继规范，ICC是一种以480/Mb/s USB 2.0规格为基础的芯片接口规范，由芯片设计厂商SMSC所开发。SMSC已开始授权这项技术，并已与高通(Qualcomm)及AMD签署协议。而新的规范则可望免费提供给主控芯片设计业者，并以10万美元的一次性费用提供给周边芯片设计厂商。

SSIC可能会免费向所有采用MIPI联盟规范的会员，以及希望将它用在芯片中的USB 3.0推动小组免费开放。未来厂商们可以在合理和非歧视(reasonable and non-discriminatory,RAND)的基础上取得这项技术授权。

市场对芯片接口的需求相当明确。由于缺乏可提供高吞吐量、低功耗链接等特性的标准，多家应用处理器供应商已经设计了自有的下一代芯片接口。

MIPI联盟希望将其M-PHY打造为通用的芯片-芯片接口。事实上，它已经被指定为六项该联盟自有或仍待审核之互连标准的技术基础。JEDEC还采用M-PHY作为其UFS闪存接口的一部分。

点击参考原文：Spec turns USB3 into chip link

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Spec turns USB3 into chip link

Rick Merritt

Two industry groups are pooling their technologies to define a new high speed, low power chip-to-chip interface for next generation mobile silicon. The USB 3.0 Promoters Group and the MIPI Alliance hope to finish and make available a joint specification early next year.

The so-called Superspeed Inter-Chip spec (SSIC) aims to support physical layer data rates starting at 1.2 to 2.9 Gbits/s and eventually extending up to 5.8 Gbits/s. It also plans a low power mode for data rates between 10 Kbits/s and 600 Mbits/s.

SSIC targets power consumption of about 1-5 picojoules per bit/second, depending on the mode used. In high-speed mode that may amount to an average of about 20 mW.

The effort essentially marries the M-PHY spec, a low power physical layer technology defined by the MIPI Alliance, with the media access controller and higher layer software of the USB 3.0 spec. A working group under the USB 3.0 Promoters Group including members of Intel, ST Ericsson and Texas Instruments started working on the details of the spec about a month ago.

The working group is now deciding what if any parts of the USB 3.0 spec to make optional because they may not be needed in a chip interface. "We wanted to lower the cost of design and time to market by leveraging existing IP—it's about software reuse," said Brian Carlson, vice chair of MIPI and Omap product manager at TI.

SSIC aims to be follow-on of Inter-Chip Connectivity (ICC), a chip interface based on the 480 Mbit/s USB 2.0 spec developed privately by chip designer SMSC (Hauppauge, NY). SMSC started licensing the technology in June and signed up Qualcomm and AMD earlier this year. It makes its spec available free to host chip designers and for a one-time $100,000 fee to peripheral chip designers.

SSIC would be royalty free to all adopter-level members of the MIPI Alliance and the USB 3.0 Promoters group who want to use it in chips for what Carlson described as "mobile terminals with voice capability," including Wi-Fi devices with VoIP features. Vendors could license the technology on a reasonable and non-discriminatory (RAND) basis for other kinds of chips or systems.

The need is clear. Multiple vendors of applications processors are already designing their own next-generation chip interfaces due to a lack of a standard for the kind of high throughput, low power link they need.

For its part, the MIPI Alliance hopes to establish its M-PHY as a general purpose chip-to-chip interface. It has already specified the technology as the basis for six of its own existing or pending interconnect standards. Jedec has also adopted M-PHY as part of its UFS flash memory interface.