英特尔“低电压弹性内存”实现处理器超低电压电路

在近日于美国夏威夷州举行的2010年超大集成电路研讨会(Symposium on VLSI Circuits)上，英特尔(Intel)将推出一种所谓的“低电压弹性内存(low-voltage resilient memories)”。

据了解，这种新技术将有助于在处理器设计中实现超低电压电路；在这个领域有一个问题是与性能不彰的缓存器(register)有关。“在CPU 中负责运作内存的缓存器很难以低电压执行，这是一个微处理器核心运作电压最小化的限制因素。”英特尔的简报指出。

为此英特尔提出了低电压弹性内存的概念，该公司表示，那是一种能耐受各种变异以及泄漏噪声的电路。英特尔指出，该种技术的电压阈值能依需求不同，设定为1V至340mV的范围；此外其能源效益据说可达到每瓦5,500亿次运作(operations per Watt)。

英特尔技术官、资深院士兼英特尔实验室总监Justin Rattner在一场电话会议中表示，低电压弹性内存将会是：“新一代低电压处理器内含的功能区块。”

在该研讨会上，英特尔还将发表另一篇论文，涉及设计校正中“复本位(replica bits)”与错误标示的问题。其简介指出：“我们提议在芯片上内存内加入复制位，在读写运作期间用以侦测并标示错误，如此就能移除电压保护带宽(voltage guard bands)。”

上述技术据说可为45纳米CMOS制程的16KB数组降低7.5%的电压。此外英特尔其他与降低耗电技术相关的论文，还包括介绍一种针对整合式数字无线电应用的数字合成器技术(digital synthesizer)，适合WPAN、WiDi、Wi-Fi与WiMax等领域。

(下一页：参考原文：Intel tips 'resilient memories' for MPUs，by Mark LaPedus)

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Intel tips 'resilient memories' for MPUs

by Mark LaPedus

At this week's 2010 Symposium on VLSI Circuits in Hawaii, Intel Corp. will describe what it calls "low-voltage resilient memories."

The technology will help enable ultra low-power circuits in processor designs. One of the problems in this arena involves the lowly register. "Registers working memories on CPU (are) very difficult to run at low voltages--(a) limiting factor for minimum operating supply voltage of a microprocessor core," according to a presentation from Intel.

To lower the power, Intel proposes to use low-voltage resilient memories, which are "circuits that are tolerant to variations and leakage noises."

This technology can be scaled from 1-Volt to near threshold at 340-mV, depending on the requirements. It is also said to have an energy-efficiency of 550 billion operations per Watt, according to Intel.

Low-voltage resilient memories "will be the building blocks" for next-generation, low-power processors, said Justin Rattner, Intel's chief technology officer, senior fellow and director at Intel Labs, in a conference call.

In separate paper, Intel tipped “replica bits” to flag errors for correction in designs. "We propose adding duplicate bits to on-chip memories to detect and flag errors during read and write operations, allowing voltage guard bands to be removed," according to the presentation.

The technology is said to enable 7.5 percent lower power for a 16-KB array in a 45-nm CMOS process, according to Intel.

In another paper related to power, Intel described a new digital synthesizer technology for integrated digital radios. "Digital frequency synthesizers have not been widely adopted for high data-rate wireless communications due to susceptibility to noise," according to Intel.

Intel’s 90-nm digital fractional-N synthesizer "overcomes these challenges, uses a self-calibrating design resulting in a resolution finer than 10-Hz," according to Intel. "Fractional-N synthesizers generate a fine frequency resolution that is a fraction of the reference frequency with low phase noise."

The technology has multi-radio applications for WPAN, WiDi, WiFi and WiMax.

On the security side, Intel has a paper on an encryption accelerator for content protection. Intel has devised a 45-nm test chip that runs at 53-Gbps, or fivefold better than the best reported work to date, Intel said.